公开(公告)号：US20200176578A1

公开(公告)日：2020-06-04

申请号：US16208288

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/11521 ,  H01L29/66 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/788

Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

公开(公告)号：US20200020789A1

公开(公告)日：2020-01-16

申请号：US16576370

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20190378548A1

公开(公告)日：2019-12-12

申请号：US16551593

申请日：2019-08-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Xian Liu ,  Nhan Do

IPC: G11C7/10 ,  H01L21/28 ,  H01L27/11521 ,  G11C8/12

Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

公开(公告)号：US20190148529A1

公开(公告)日：2019-05-16

申请号：US16245069

申请日：2019-01-10

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chieng-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L49/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/788

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20190080753A1

公开(公告)日：2019-03-14

申请号：US15701071

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.

公开(公告)号：US20170338330A1

公开(公告)日：2017-11-23

申请号：US15494499

申请日：2017-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L29/42328

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20160254269A1

公开(公告)日：2016-09-01

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract translation: 一种存储器件，其包括多个ROM单元，每个ROM单元具有形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，设置在沟道区域的第一部分上方并与沟道区域的第一部分绝缘的第一栅极， 与沟道区的第二部分绝缘，以及在多个ROM单元上延伸的导电线。 导电线电耦合到ROM单元的第一子组的漏极区域，并且不电耦合到ROM单元的第二子组的漏极区域。 或者，ROM单元的第一子组各自包括沟道区域中的较高电压阈值注入区域，而ROM单元的第二子组每个在沟道区域中都缺少任何较高电压阈值注入区域。

公开(公告)号：US20160217849A1

公开(公告)日：2016-07-28

申请号：US15002302

申请日：2016-01-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

IPC: G11C11/419 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

CPC classification number: G11C11/419 ,  G11C16/0458 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

Abstract translation: 一种形成存储器件的方法，包括在衬底上形成第一绝缘层，第一导电层，第二绝缘层，第二导电层，第三绝缘层。 第一沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分露出。 第一绝缘层形成在沿第一导电层的暴露部分延伸的第一沟槽的底部。 第一个沟槽填充有导电材料。 第二沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成。 在第二沟槽下的衬底中形成漏区。 导致一对存储单元，其中单个连续沟道区域在用于该对存储单元的漏极区域之间延伸。

公开(公告)号：US09293204B2

公开(公告)日：2016-03-22

申请号：US14252929

申请日：2014-04-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

IPC: H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423

CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

公开(公告)号：US20140104961A1

公开(公告)日：2014-04-17

申请号：US13466878

申请日：2012-05-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract translation: 非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。 每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。