公开(公告)号：US20240329302A1

公开(公告)日：2024-10-03

申请号：US18741308

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Jiun Yi Wu ,  Hung-Yi Kuo ,  Shang-Yun Hou

IPC: G02B6/12 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H01L31/02 ,  H01L31/0232

CPC classification number: G02B6/12004 ,  H01L24/19 ,  H01L24/20 ,  H01L25/167 ,  H01L25/18 ,  H01L31/02002 ,  H01L31/02327 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/211 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

公开(公告)号：US12038599B2

公开(公告)日：2024-07-16

申请号：US17340363

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Jiun Yi Wu ,  Hung-Yi Kuo ,  Shang-Yun Hou

IPC: G02B6/12 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H01L31/02 ,  H01L31/0232

CPC classification number: G02B6/12004 ,  H01L24/19 ,  H01L24/20 ,  H01L25/167 ,  H01L25/18 ,  H01L31/02002 ,  H01L31/02327 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/211 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

公开(公告)号：US12021053B2

公开(公告)日：2024-06-25

申请号：US17832949

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

公开(公告)号：US11935761B2

公开(公告)日：2024-03-19

申请号：US17458854

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L21/565 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/73267

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

公开(公告)号：US11848304B2

公开(公告)日：2023-12-19

申请号：US17869034

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Shang-Yun Hou

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/97 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49861 ,  H01L2224/80895 ,  H01L2224/82896

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

公开(公告)号：US11848234B2

公开(公告)日：2023-12-19

申请号：US17412625

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/76 ,  H01L21/48 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/76895 ,  H01L21/486 ,  H01L21/561 ,  H01L24/05 ,  H01L24/19 ,  H01L24/32 ,  H01L24/33 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2924/181

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.

公开(公告)号：US11837567B2

公开(公告)日：2023-12-05

申请号：US17186775

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/29 ,  H01L23/14 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/14104 ,  H01L2224/211 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/2902 ,  H01L2224/8134 ,  H01L2224/8234 ,  H01L2924/35

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

公开(公告)号：US11756945B2

公开(公告)日：2023-09-12

申请号：US17186726

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/17177

Abstract: A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.

公开(公告)号：US20230260862A1

公开(公告)日：2023-08-17

申请号：US18302589

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L23/5384 ,  H01L23/49827

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

公开(公告)号：US20230253378A1

公开(公告)日：2023-08-10

申请号：US18302165

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chien-Hsun Lee ,  Jiun Yi Wu

IPC: H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L25/105 ,  H01L23/3121 ,  H01L25/0655 ,  H01L24/08 ,  H01L23/49822 ,  H01L25/50 ,  H01L21/561 ,  H01L21/4857 ,  H01L23/367 ,  H01L24/94 ,  H01L2224/08225 ,  H01L2225/1058 ,  H01L2225/1023

Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.