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218 条记录 (耗时 0.029 秒)

    High-speed data programmable nonvolatile semiconductor memory device
    81.
    发明授权
    High-speed data programmable nonvolatile semiconductor memory device 有权
    高速数据可编程非易失性半导体存储器件

    公开(公告)号：US06762956B2

    公开(公告)日：2004-07-13

    申请号：US10241029

    申请日：2002-09-11

    申请人： Seiichi Mori ,  Toru Tanzawa

    发明人： Seiichi Mori ,  Toru Tanzawa

    IPC分类号： G11C1604

    CPC分类号： G11C16/107 ,  G11C16/14 ,  G11C2216/18

    摘要： A semiconductor integrated circuit device includes a memory block. The device performs a programming operation, a pre-programming operation, and an erasing operation. The pre-programming operation by which each of the nonvolatile memory cells in the erased state in the memory block including the nonvolatile memory cells is pre-programmed to an intermediate state between the programmed and erased states.

    摘要翻译： 半导体集成电路装置包括存储块。 该装置执行编程操作，预编程操作和擦除操作。 在包括非易失性存储单元的存储器块中被擦除状态的每个非易失性存储单元被预编程到编程和擦除状态之间的中间状态的预编程操作。

    Channel-erase nonvolatile semiconductor memory device
    82.
    发明授权
    Channel-erase nonvolatile semiconductor memory device 有权

    公开(公告)号：US06577538B2

    公开(公告)日：2003-06-10

    申请号：US10197847

    申请日：2002-07-19

    申请人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

    发明人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

    IPC分类号： G11C1604

    CPC分类号： G11C16/16 ,  G11C2216/18

    摘要： In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

    Semiconductor storage apparatus
    83.
    发明授权
    Semiconductor storage apparatus 失效

    公开(公告)号：US06552936B2

    公开(公告)日：2003-04-22

    申请号：US10052303

    申请日：2002-01-18

    申请人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

    发明人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

    IPC分类号： G11C1604

    CPC分类号： G11C7/1021 ,  G11C8/10

    摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

    Boosted voltage generating circuit and semiconductor memory device having the same
    84.
    发明授权
    Boosted voltage generating circuit and semiconductor memory device having the same 失效

    公开(公告)号：US06487120B2

    公开(公告)日：2002-11-26

    申请号：US09864181

    申请日：2001-05-25

    申请人： Toru Tanzawa ,  Takeshi Miyaba ,  Shigeru Atsumi

    发明人： Toru Tanzawa ,  Takeshi Miyaba ,  Shigeru Atsumi

    IPC分类号： G11C1604

    CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C5/147 ,  G11C16/12 ,  G11C16/30

    摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

    Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods
    86.
    发明授权
    Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods 有权
    具有多层具有外围晶体管的存储单元的半导体装置及方法

    公开(公告)号：US08860117B2

    公开(公告)日：2014-10-14

    申请号：US13096822

    申请日：2011-04-28

    申请人： Toru Tanzawa

    发明人： Toru Tanzawa

    IPC分类号： H01L27/108 ,  H01L27/115 ,  G11C8/10

    CPC分类号： H01L27/11582 ,  G11C8/10 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/495 ,  H01L29/4966

    摘要： Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

    摘要翻译： 公开了装置和方法，包括包括多个第一半导体材料层的装置，每个层包括至少一个存储单元的至少一个存取线和至少一个至少一个的至少一个源极，沟道和/或漏极 外围晶体管，例如在接入线解码器电路或数据线复用电路中使用的晶体管。 该装置还可以包括延伸穿过第一半导体材料层的第二半导体材料的多个支柱，每个支柱包括至少一个存储器单元的源极，沟道和/或漏极，或者在 至少一个外围晶体管。 还描述了形成这种装置的方法以及其他实施例。

    MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES
    88.
    发明申请
    MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES 有权

    公开(公告)号：US20140056049A1

    公开(公告)日：2014-02-27

    申请号：US13590964

    申请日：2012-08-21

    申请人： Toru Tanzawa

    发明人： Toru Tanzawa

    IPC分类号： G11C5/06

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    摘要： Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described.

    CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY
    89.
    发明申请
    CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY 有权
    CHUNK REDUNDANCY建筑记忆

    公开(公告)号：US20130332674A1

    公开(公告)日：2013-12-12

    申请号：US13995169

    申请日：2012-03-29

    申请人： Toru Tanzawa

    发明人： Toru Tanzawa

    IPC分类号： G06F11/10 ,  G06F3/06

    CPC分类号： G06F11/2094 ,  G06F3/0689 ,  G06F11/1076 ,  G06F11/2017 ,  G06F2201/805 ,  G06F2201/82 ,  G11C29/82

    摘要： An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.

    摘要翻译： 集成电路（IC）包括可寻址的存储器块和至少一个冗余的存储器块。 存储器块包括两个或更多个存储器块。 IC还包括冗余控制单元。 控制电路被包括以代替存储器的可寻址块中的第一重新映射的块之一来访问冗余的存储器块，并且代替存储器的冗余块的第二块代替第二重新映射的块 基于冗余控制单元的可寻址存储块。