公开(公告)号：US09040399B2

公开(公告)日：2015-05-26

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L21/425 ,  H01L29/66

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US08803243B2

公开(公告)日：2014-08-12

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L21/70

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US08673757B2

公开(公告)日：2014-03-18

申请号：US12913795

申请日：2010-10-28

申请人： William K. Henson

发明人： William K. Henson

IPC分类号： H01L21/02

CPC分类号： H01L27/092 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203

摘要： A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.

摘要翻译： 提供了一种方法，其包括在衬底的第一部分上的至少第一导电类型半导体器件上形成高k电介质蚀刻停止层，以及在半导体器件的第二部分上形成至少第二导电类型半导体器件。 在第一导电类型半导体器件和第二导电类型半导体器件上沉积第一应力诱导层。 然后通过对高k电介质蚀刻停止层选择性的蚀刻去除形成在第二导电类型半导体器件上的第一应力诱导层的部分，以提供基板的第二部分的暴露表面，其包括 至少第二导电型半导体器件。 然后在第二导电类型半导体器件上形成第二应力诱导层。

公开(公告)号：US20130087859A1

公开(公告)日：2013-04-11

申请号：US13253268

申请日：2011-10-05

申请人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

发明人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

IPC分类号： H01L21/266 ,  H01L27/092

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517

摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

摘要翻译： 一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。 在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。 还公开了形成上述装置的方法。

公开(公告)号：US08350341B2

公开(公告)日：2013-01-08

申请号：US12757323

申请日：2010-04-09

申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

IPC分类号： H01L21/02

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。

公开(公告)号：US20120208337A1

公开(公告)日：2012-08-16

申请号：US13456633

申请日：2012-04-26

申请人： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

发明人： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

摘要翻译： 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08030709B2

公开(公告)日：2011-10-04

申请号：US11954918

申请日：2007-12-12

申请人： Charlotte D. Adams ,  Bruce B. Doris ,  Philip Fisher ,  William K. Henson ,  Jeffrey W. Sleight

发明人： Charlotte D. Adams ,  Bruce B. Doris ,  Philip Fisher ,  William K. Henson ,  Jeffrey W. Sleight

IPC分类号： H01L21/70 ,  H01L27/148 ,  H01L27/12 ,  H01L21/84 ,  H01L21/338

CPC分类号： H01L29/4983 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.

摘要翻译： 包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。 还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。 在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。 除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。 在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

公开(公告)号：US08004059B2

公开(公告)日：2011-08-23

申请号：US11622616

申请日：2007-01-12

申请人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

发明人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

公开(公告)号：US07960809B2

公开(公告)日：2011-06-14

申请号：US12354996

申请日：2009-01-16

申请人： Chandrasekharan Kothandaraman ,  Deok-kee Kim ,  Dureseti Chidambarrao ,  William K. Henson

发明人： Chandrasekharan Kothandaraman ,  Deok-kee Kim ,  Dureseti Chidambarrao ,  William K. Henson

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.

摘要翻译： 熔丝包括熔丝链接区域，第一区域和第二区域。 熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。

公开(公告)号：US07943460B2

公开(公告)日：2011-05-17

申请号：US12426457

申请日：2009-04-20

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。