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    Fin type field effect transistors and methods of manufacturing the same
    84.
    发明申请
    Fin type field effect transistors and methods of manufacturing the same 有权
    鳍式场效应晶体管及其制造方法

    公开(公告)号：US20060189058A1

    公开(公告)日：2006-08-24

    申请号：US11359000

    申请日：2006-02-22

    申请人： Jong-Wook Lee ,  Deok-Hyung Lee ,  Min-Gu Kang ,  Yu-Gyun Shin

    发明人： Jong-Wook Lee ,  Deok-Hyung Lee ,  Min-Gu Kang ,  Yu-Gyun Shin

    IPC分类号： H01L21/8234 ,  H01L29/76

    CPC分类号： H01L29/78618 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.

    摘要翻译： 鳍型场效应晶体管包括半导体衬底，有源鳍，第一硬掩模层图案，栅极绝缘层图案，第一导电层图案和源极/漏极区域。 活性鳍片包括半导体材料，并且形成在基底上并沿远离基底的主表面的方向延伸。 第一硬掩模层图案形成在有源鳍片的远离表面上的基底上。 栅极绝缘层形成在有源鳍片的侧壁部分上。 第一导电层图案包括金属硅化物，并且形成在基板和栅极绝缘层图案的表面上，以及在第一硬掩模图案的侧壁上。 源极/漏极区域形成在第一导电层图案的相对侧上的有源鳍片中。

    Semiconductor device and method of fabricating the same
    85.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US07611934B2

    公开(公告)日：2009-11-03

    申请号：US11182150

    申请日：2005-07-15

    申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

    MOSFET formed on a strained silicon layer
    86.
    发明授权
    MOSFET formed on a strained silicon layer 有权
    形成在应变硅层上的MOSFET

    公开(公告)号：US07557388B2

    公开(公告)日：2009-07-07

    申请号：US11398118

    申请日：2006-04-05

    申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    IPC分类号： H01L31/00 ,  H01L35/26 ,  H01L31/117

    CPC分类号： C30B29/06 ,  C30B15/00

    摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

    摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

    Fin field effect transistor and method of manufacturing the same
    87.
    发明申请
    Fin field effect transistor and method of manufacturing the same 有权
    Fin场效应晶体管及其制造方法

    公开(公告)号：US20060118876A1

    公开(公告)日：2006-06-08

    申请号：US11292261

    申请日：2005-11-30

    申请人： Deok-Hyung Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Min-Gu Kang

    发明人： Deok-Hyung Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Min-Gu Kang

    IPC分类号： H01L21/338 ,  H01L29/76

    CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.

    摘要翻译： 在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。 第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。 在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。 在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。 可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

    Semiconductor device and method of fabricating the same
    89.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06975001B2

    公开(公告)日：2005-12-13

    申请号：US10163984

    申请日：2002-06-06

    申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

    摘要翻译： 半导体器件包括（a）形成在电绝缘层上的半导体层，（b）形成在半导体层上的栅极绝缘膜，（c）形成在栅极绝缘膜上的栅电极，以及（d）场绝缘 在半导体层上形成用于限定要制造半导体器件的区域的膜。 半导体层包括（a1）形成在栅极周围的半导体层中的源极和漏极区，源极和漏极区包含第一导电型杂质，（a2）形成在半导体层中的体接触区域， 包含第二导电型杂质，以及（a3）形成在半导体层中的载流子路径区域，使得载流子路径区域不与源区域和漏极区域接触，但与体接触区域接触，载体路径区域 含有第二导电型杂质。