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公开(公告)号：US09553717B2
公开(公告)日：2017-01-24
申请号：US14218697
申请日：2014-03-18
CPC分类号： H04L7/0331 , H03L7/07 , H03L7/0807 , H04L7/0016 , H04L7/046 , H04L7/10
摘要： Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.
摘要翻译： 公开了用于时钟和数据恢复的装置和方法。 复位电路对输入信号的边沿之间的时钟周期进行计数，并且当时钟周期计数超出范围时，复位执行数据流的采集和跟踪的信号处理电路。 信号处理电路还被配置为根据校正的数据速率执行采集和跟踪，该数据速率可以通过相位误差校正控制环路的数据速率调整和/或两个数据速率之间的抖动来产生。
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公开(公告)号：US20170011261A1
公开(公告)日：2017-01-12
申请号：US14794991
申请日：2015-07-09
申请人： Raka Singh
发明人： Raka Singh
CPC分类号： G06K9/00369 , G06K9/00771 , G06K9/00832 , G06T2207/10016 , G06T2207/30196
摘要： Many conventional video processing algorithms attempting to detect human presence in a video stream often generate false positives on non-human movements such as plants moving in the wind, rotating fan, etc. To reduce false positives, a technique exploiting temporal correlation of non-human movements can accurately detect human occupancy while reject non-human movements. Specifically, the technique involves performing temporal analysis on a time-series signal generated based on an accumulation of foreground maps and an accumulation of motion map and analyzing the running mean and the running variance of the time-series signal. By determining whether the time-series signal is correlated in time, the technique is able to distinguish human movements and non-human movements. Besides having superior accuracy, the technique lends itself to an efficient algorithm which can be implemented on low cost, low power digital signal processor or other suitable hardware.
摘要翻译： 试图在视频流中检测人类存在的许多传统视频处理算法通常在诸如在风中运动的植物，旋转风扇等非人类运动上产生假阳性。为了减少误报，一种利用非人类时间相关性的技术 运动可以准确地检测人的占用，同时拒绝非人类的运动。 具体地说，该技术涉及对基于前景地图的积累和运动图的积累而生成的时间序列信号进行时间分析，并分析时间序列信号的运行平均值和运行方差。 通过确定时间序列信号是否与时间相关，该技术能够区分人类运动和非人类运动。 除了具有更高的精度外，该技术还适用于可在低成本，低功耗数字信号处理器或其他合适的硬件上实现的高效算法。
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83.发明授权DC linear voltage regulator comprising a switchable circuit for leakage current suppression 有权DC线性稳压器包括用于泄漏电流抑制的可切换电路公开(公告)号：US09513647B2
公开(公告)日：2016-12-06
申请号：US14673137
申请日：2015-03-30
CPC分类号： G05F1/575
摘要： The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.
摘要翻译： 本发明在一个方面涉及一种用于基于直流输入电压产生稳定的直流输出电压的直流线性稳压器电路。 DC线性稳压器电路包括DMOS传输晶体管，其包括漏极，栅极，源极和体积端子，其中漏极端子连接到调节器输出，该稳压器输出被配置为提供稳压的DC输出电压，并且源极端子连接到调节器输入 用于接收直流输入电压。 直流线性稳压器电路包括可切换的防漏电路，连接到DMOS传输晶体管的批量端子，并被配置为自动检测和中断从稳压器输出到散装端子的泄漏电流。
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公开(公告)号：US20160349326A1
公开(公告)日：2016-12-01
申请号：US14721152
申请日：2015-05-26
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G01R31/31705
摘要： A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.
摘要翻译： 诸如片上系统的系统具有非调试域和调试域。 调试域具有调试框架，可以调试器驱动，非调试域系统重置。 该系统包括复位控制单元和调试触发机制，其包括连接到复位控制单元的调试触发接口（DTI）。 DTI配置为触发复位控制单元以重置非调试域。 还可以将DTI配置为监视非调试域系统重置的状态。
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公开(公告)号：US09448579B2
公开(公告)日：2016-09-20
申请号：US14136774
申请日：2013-12-20
发明人： Stefan Marinca
IPC分类号： G05F3/18
CPC分类号： G05F3/185
摘要： Circuits and method for providing voltage reference circuits that include low drift over time and lower operating voltages are provided. Generally, it is desirable that a reference circuit provide an accurate and precise reference over time. The voltage reference circuits described can provide for good long term stability, operation at lower voltages than prior designs, consistent output voltage with reduced variability due to process changes and mismatches, low noise in the reference voltage, and other advantages.
摘要翻译： 提供用于提供包括随时间的低漂移和较低工作电压的电压参考电路的电路和方法。 通常，期望参考电路随时间提供精确和精确的参考。 所描述的电压参考电路可以提供良好的长期稳定性，在比以前的设计更低的电压下操作，一致的输出电压由于过程变化和不匹配而降低的可变性，参考电压中的低噪声以及其它优点。
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公开(公告)号：US09444487B1
公开(公告)日：2016-09-13
申请号：US14838097
申请日：2015-08-27
发明人： Dennis A. Dempsey
摘要： In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.
摘要翻译： 在一个示例中，公开了一种多级数模转换器，包括：第一级具有第一组电路部件，第二级具有第二组电路部件，第三级具有第三组电路部件 第三级在第一和第二可转换的阻抗路径内提供负载; 其中所述DAC可在第一模式，第二模式和第三操作模式中的每一个中操作，其中在第一模式中，所述第一级可独立于所述第三级可切换地耦合到所述第二级; 在第二模式中，负载被耦合并呈现给电路部件的第二级的第一部分，并且在第三模式中，负载耦合并呈现给第二级电路部件的第二，不同部分。 还公开了相应的系统和方法。
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公开(公告)号：US09444444B2
公开(公告)日：2016-09-13
申请号：US13958141
申请日：2013-08-02
发明人： Takashi Fujita
IPC分类号： H03K17/16 , H03K17/042
CPC分类号： H03K17/165 , H03K17/04206 , H03K17/163 , H03K17/166
摘要： A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.
摘要翻译： 驱动器可以在两个阶段中在开状态和断开状态之间提供开关的转换。 在第一阶段中，可以控制开关输出端的电压的电压转换速率。 在第二阶段，可以控制开关的电流梯度。 可以基于开关的输出端子处的电压值来进行第一级和第二级之间的转换。
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88.发明申请METHOD AND APPARATUS FOR PROVIDING INPUT TO A CAMERA SERIAL INTERFACE TRANSMITTER 有权用于向摄像机串行接口发射器输入的方法和装置公开(公告)号：US20160212456A1
公开(公告)日：2016-07-21
申请号：US14598299
申请日：2015-01-16
IPC分类号： H04N21/236 , B60R11/04 , H04N21/234 , H04N21/4223 , H04N21/2365 , H04N21/414 , H04H20/62
CPC分类号： H04N21/23602 , B60R11/04 , G06F13/38 , G06F13/4291 , H04H20/62 , H04L1/0057 , H04L25/4904 , H04L25/493 , H04N7/18 , H04N7/181 , H04N21/23406 , H04N21/2365 , H04N21/41422 , H04N21/4223 , Y02D10/14 , Y02D10/151
摘要： A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.
摘要翻译： 公开了一种用于接收至少两个数据流并向MIPI的CSI Tx提供单个输入数据流的系统。 两个接收的数据流被写入相应的数据缓冲器。 该系统包括控制逻辑，其被配置为控制将存储在缓冲器中的数据读取到多路复用器，读侧时钟是固定频率时钟频率的倍数。 控制逻辑还被配置为控制多路复用器将从与完整数据单元对应的每个缓冲器读取的数据组合成单独的部分，并将分离的部分复用到输入数据流中。 以这种方式，可以使用单个CSI Tx发送两个数据流。 当系统从APIX接口接收到两个数据流时，系统提供了APIX接口和MIPI的CSI Tx之间的桥梁。
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公开(公告)号：US09391628B1
公开(公告)日：2016-07-12
申请号：US14967880
申请日：2015-12-14
发明人： Colin G. Lyden , Pasquale Delizia , Sanjay Rajasekhar , Yogesh Jayarman Sharma , Arthur J. Kalb , Marvin L. Shu , Gerard Mora-Puchalt , Roberto S. Maurino
CPC分类号： H03M1/1245 , G11C27/026
摘要： An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.
摘要翻译： 模数转换器（ADC）的输入级包括至少一个用于采集相位中的输入信号的采样电容器（SC），用于向SC提供输入信号的电容增益放大器（CGA）以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽，并且在所述获取阶段的后续，第二部分期间具有第二带宽，第二带宽小于第一带宽。 以这种方式，首先，以更高的第一带宽对输入信号进行采样，从而可利用使用高带宽CGA来最小化SC上的稳定误差，并且接下来在相同获取阶段的第二部分期间 ，输入信号以较低，第二带宽进行采样，有利于降低使用高带宽CGA导致的噪声。
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公开(公告)号：US09391578B2
公开(公告)日：2016-07-12
申请号：US14302223
申请日：2014-06-11
发明人： Muhammad Kalimuddin Khan , Michael J. Deeney , Niall Kevin Kearney , Kenneth J. Mulvaney , Shane A. O'Mahony
CPC分类号： H03G3/3052 , H03G3/3068 , H04B1/30 , H04B2001/305
摘要： An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.
摘要翻译： LIF接收机包括：接收机路径，包括：混合器，用于将接收到的RF信号与本地振荡器信号混合，以提供比所接收的RF信号低的频率的IF信号;滤波IF信号的带通滤波器;用于放大的PGA 经滤波的IF信号，用于将放大的滤波IF信号转换为数字信号的ADC，用于将数字信号转换为基带数字信号的转换器，以及响应于接收到的幅度的设定PGA的增益的AGC 射频信号。 可编程DC信号源将经编程的DC偏移信号注入由ADC转换的经放大的经滤波的IF信号中，并且在PGA之后可操作地连接到接收器路径的信号传感器确定编程的DC偏移信号的PGA信号输出的极性 。 控制器确定在没有接收的RF信号的情况下使PGA的至少一个增益设置最小化基带信号幅度的编程的DC偏移信号。
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