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377 条记录 (耗时 0.023 秒)

    High voltage selector circuit with no quiescent current
    81.
    发明授权
    High voltage selector circuit with no quiescent current 有权

    公开(公告)号：US09685938B2

    公开(公告)日：2017-06-20

    申请号：US15019394

    申请日：2016-02-09

    申请人： LINEAR TECHNOLOGY CORPORATION

    发明人： Ciaran J. Brennan ,  Mukesh Kumar

    IPC分类号： H03K17/00 ,  H03K5/1532 ,  H01L27/088

    CPC分类号： H03K5/1532 ,  H01L27/0883

    摘要： A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

    Squelch detector
    85.
    发明授权
    Squelch detector 有权
    静噪探测器

    公开(公告)号：US09360505B1

    公开(公告)日：2016-06-07

    申请号：US14798932

    申请日：2015-07-14

    申请人： GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Ju-Chieh Wang ,  Ting-Hsu Chien ,  Da-Rong Huang

    IPC分类号： G01R19/165 ,  H03K5/1532 ,  H03K5/24

    CPC分类号： G01R19/165 ,  G01R19/1659 ,  H03G3/34 ,  H03K5/1532 ,  H03K5/2481

    摘要： A squelch detector receives a first input signal, a second input signal, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal pair. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal pair is valid or not.

    摘要翻译： 静噪检测器接收第一输入信号，第二输入信号，第一参考电压和第二参考电压。 协作地将第一输入信号和第二输入信号定义为差分输入信号对。 第一参考电压和第二参考电压之间的差被定义为静噪阈值。 根据静噪阈值，静噪检测器产生检测信号，以指示差分输入信号对是否有效。

    HIGH VOLTAGE SELECTOR CIRCUIT WITH NO QUIESCENT CURRENT
    86.
    发明申请
    HIGH VOLTAGE SELECTOR CIRCUIT WITH NO QUIESCENT CURRENT 有权
    高电压选择电路，无杂质电流

    公开(公告)号：US20160156341A1

    公开(公告)日：2016-06-02

    申请号：US15019394

    申请日：2016-02-09

    申请人： LINEAR TECHNOLOGY CORPORATION

    发明人： Ciaran J. Brennan ,  Mukesh Kumar

    IPC分类号： H03K5/1532 ,  H01L27/088

    CPC分类号： H03K5/1532 ,  H01L27/0883

    摘要： A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

    摘要翻译： 最大电压选择电路可以包括多个输入，每个用于接收不同的输入电压，用于输送最高输入电压的输出，以及电压选择电路。 电压选择电路可以自动选择具有最大电压幅值的输入端，将所选输入端的电压自动输出到输出端，并且不从任何输入端抽取静态工作电流。 对于多个输入中的两个的每个独特组合，电压选择电路可以包括增强型FET，其中通道串联连接在两个输入的唯一组合的第一输入和输出之间; 增强型FET的栅极与通过耗尽型FET的沟道的两个输入的独特组合的第二输入端之间的连接; 一个附加的增强型FET，其中通道串联在第二个两个输入和输出的唯一组合之间; 以及附加增强型FET的栅极和通过附加耗尽型FET的沟道的两个输入的唯一组合中的第一个之间的连接。

    COMBINATION AC/DC PEAK DETECTOR AND SIGNAL TYPE DISCRIMINATOR
    88.
    发明申请
    COMBINATION AC/DC PEAK DETECTOR AND SIGNAL TYPE DISCRIMINATOR 有权
    组合AC / DC峰值检测器和信号类型分辨率

    公开(公告)号：US20100007384A1

    公开(公告)日：2010-01-14

    申请号：US12499631

    申请日：2009-07-08

    申请人： Lev Michael Barsky

    发明人： Lev Michael Barsky

    IPC分类号： H03K5/1532

    CPC分类号： H03K5/1532 ,  G01R19/04

    摘要： A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein the positive-side Schmitt trigger is configured to receive an output provided by the input stage, and wherein the positive-side Schmitt trigger is configured to create a positive-side Schmitt trigger output representative of the current input, and a negative-side Schmitt trigger in communication with the input stage, wherein the negative-side Schmitt trigger is configured to receive the output provided by the input stage, and wherein the negative-side Schmitt trigger is configured to create a negative-side Schmitt trigger output representative of the current input.

    摘要翻译： 公开了一种用于电流检测和鉴别的装置和方法。 该装置包括：差分接收器，被配置为接收电流输入;与输入级通信的正侧施密特触发器，其中正侧施密特触发器被配置为接收由输入级提供的输出， 侧施密特触发器被配置为创建代表电流输入的正侧施密特触发器输出，以及与输入级通信的负侧施密特触发器，其中负侧施密特触发器被配置为接收由输入端提供的输出 输入级，并且其中负侧施密特触发器被配置为产生代表电流输入的负侧施密特触发器输出。

    Method and apparatus for signal processing in a sensor system for use in spectroscopy
    89.
    发明申请
    Method and apparatus for signal processing in a sensor system for use in spectroscopy 有权
    用于光谱学的传感器系统中的信号处理方法和装置

    公开(公告)号：US20050246140A1

    公开(公告)日：2005-11-03

    申请号：US10835092

    申请日：2004-04-29

    申请人： Paul O'Connor ,  Gianluigi DeGeronimo ,  Joseph Grosholz

    发明人： Paul O'Connor ,  Gianluigi DeGeronimo ,  Joseph Grosholz

    IPC分类号： G01J1/42 ,  G01J1/44 ,  G01J3/28 ,  G01R19/04 ,  H03K5/1532 ,  H03K9/08

    CPC分类号： H03K5/1532 ,  G01J1/44 ,  G01J3/2803 ,  G01J2001/4238 ,  G01R19/04

    摘要： A method for processing pulses arriving randomly in time on at least one channel using multiple peak detectors includes asynchronously selecting a non-busy peak detector (PD) in response to a pulse-generated trigger signal, connecting the channel to the selected PD in response to the trigger signal, and detecting a pulse peak amplitude. Amplitude and time of arrival data are output in first-in first-out (FIFO) sequence. An apparatus includes trigger comparators to generate the trigger signal for the pulse-receiving channel, PDs, a switch for connecting the channel to the selected PD, and logic circuitry which maintains the write pointer. Also included, time-to-amplitude converters (TACs) convert time of arrival to analog voltage and an analog multiplexer provides FIFO output. A multi-element sensor system for spectroscopy includes detector elements, channels, trigger comparators, PDs, a switch, and a logic circuit with asynchronous write pointer. The system includes TACs, a multiplexer and analog-to-digital converter.

    摘要翻译： 一种用于处理使用多个峰值检测器在至少一个信道上随机随机到达的脉冲的方法包括响应于脉冲产生的触发信号来异步地选择非忙峰值检测器（PD），以响应于所选择的PD将信道连接到所选择的PD 触发信号，并检测脉冲峰值振幅。 幅度和到达时间数据以先进先出（FIFO）序列输出。 一种装置包括触发比较器，用于产生用于脉冲接收通道的触发信号，PD，用于将通道连接到所选择的PD的开关，以及维持写指针的逻辑电路。 还包括时间到幅度转换器（TAC）将到达时间转换为模拟电压，模拟多路复用器提供FIFO输出。 用于光谱的多元素传感器系统包括检测器元件，通道，触发比较器，PD，开关和具有异步写指针的逻辑电路。 该系统包括TAC，多路复用器和模数转换器。

    High speed flip-flops and complex gates using the same
    90.
    发明申请
    High speed flip-flops and complex gates using the same 有权
    高速触发器和使用相同的复合门

    公开(公告)号：US20050225372A1

    公开(公告)日：2005-10-13

    申请号：US11095187

    申请日：2005-03-31

    申请人： Min-su Kim

    发明人： Min-su Kim

    IPC分类号： H03K3/3562 ,  H03K3/012 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K5/1532 ,  H03K19/096 ,  H03K19/20

    CPC分类号： H03K3/012 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/20

    摘要： In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal. A logic level of a second intermediate node between the fourth PMOS transistor and the fifth NMOS transistor is latched by a second latch. Accordingly, intermediate nodes of the flip-flops are connected to ground voltages via two NMOS transistors upon logic level switching, rather than three or more, so that the switching time of the device is shortened.

    摘要翻译： 在使用其的高速触发器和复合栅极中，触发器包括串联连接在电源电压和接地电压之间的第一PMOS晶体管和第二和第三NMOS晶体管。 第一PMOS晶体管和第二NMOS晶体管的栅极连接到输入数据。 第三NMOS晶体管的栅极连接到时钟脉冲信号。 第一PMOS晶体管和第二NMOS晶体管之间的第一中间节点的逻辑电平由第一锁存器锁存。 触发器还包括串联连接在电源电压和接地电压之间的第四PMOS晶体管和第五和第六NMOS晶体管。 第四PMOS晶体管和第五NMOS晶体管的栅极连接到第一中间节点。 第六个NMOS晶体管的栅极连接到时钟脉冲信号。 第四PMOS晶体管和第五NMOS晶体管之间的第二中间节点的逻辑电平由第二锁存器锁存。 因此，触发器的中间节点在逻辑电平切换而不是三个或更多时通过两个NMOS晶体管连接到接地电压，从而缩短了器件的切换时间。