MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    1.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号:US20100261294A1

    公开(公告)日:2010-10-14

    申请号:US12543179

    申请日:2009-08-18

    IPC分类号: H01L21/02

    摘要: After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.

    摘要翻译: 在通过干蚀刻在层间绝缘膜中形成通向导电铁电电容器结构的第一通孔之后,在氢扩散防止膜中形成用于暴露部分铁电电容器结构的第二通孔,以便与第一通孔 通过湿蚀刻形成通孔,并且形成由第一通孔和第二通孔构成的通孔,彼此连通。

    Semiconductor memory and operating method of same
    2.
    发明授权
    Semiconductor memory and operating method of same 有权
    半导体存储器及其操作方法相同

    公开(公告)号:US07633831B2

    公开(公告)日:2009-12-15

    申请号:US11797816

    申请日:2007-05-08

    申请人: Hitoshi Ikeda

    发明人: Hitoshi Ikeda

    IPC分类号: G11C8/00

    摘要: An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, upon receipt of the next access command during activation of the chip enable signal. For this reason, two types of access operations whose access times differ can be carried out by receiving the same access command at the same access terminal. A dedicated terminal for distinguishing between the two types of operations does not need to be formed in a controller, etc., which accesses a semiconductor memory. Selective use of the first and second access operations improves the operation efficiency of the semiconductor memory. Consequently, the operation efficiency of the semiconductor memory can be improved without increasing the cost of a system incorporating the semiconductor memory.

    摘要翻译: 操作控制电路在激活芯片使能信号期间接收到第一访问命令时执行第一访问操作,并且在接收到第一访问操作时,在比第一访问操作更短的时间内执行访问存储器核心的第二访问操作 激活芯片使能信号时的下一个访问命令。 为此,可以通过在同一接入终端接收相同的访问命令来执行访问时间不同的两种访问操作。 用于区分两种操作的专用终端不需要形成在访问半导体存储器的控制器等中。 选择性地使用第一和第二访问操作提高了半导体存储器的操作效率。 因此,可以提高半导体存储器的操作效率,而不会增加结合半导体存储器的系统的成本。

    Charge loss restoration method and semiconductor memory device
    4.
    发明授权
    Charge loss restoration method and semiconductor memory device 失效
    充电损耗恢复方法和半导体存储器件

    公开(公告)号:US07583536B2

    公开(公告)日:2009-09-01

    申请号:US12003985

    申请日:2008-01-04

    申请人: Osamu Iioka Naoto Emi

    发明人: Osamu Iioka Naoto Emi

    IPC分类号: G11C11/34

    CPC分类号: G11C16/3418 G11C16/105

    摘要: A charge loss restoration method detects a memory cell having a tendency of a charge loss within a memory cell array of an electrically writable and erasable nonvolatile semiconductor memory device, using a charge loss detecting reference cell having a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell, where the threshold value of the write verify reference cell is higher than the threshold value of the read reference cell, and restores the memory cell having the tendency of the charge loss by making an additional write thereto.

    摘要翻译: 电荷损失恢复方法使用电荷损失检测参考单元检测具有电可写和可擦除非易失性半导体存储器件的存储单元阵列内的电荷损失趋势的存储单元,所述电荷损失检测参考单元具有设定在阈值 读取参考单元和写入验证参考单元的阈值,其中写入验证参考单元的阈值高于读取的参考单元的阈值,并且通过使得读取参考单元恢复具有电荷损失趋势的存储单元, 附加写入。

    Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero
    5.
    发明授权
    Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero 失效
    延迟输出信号的相位的延迟时间调整方法,直到输入信号和输出信号之间的相位差成为零以外的周期的整数

    公开(公告)号:US07667509B2

    公开(公告)日:2010-02-23

    申请号:US11395130

    申请日:2006-04-03

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0814 H03L7/085

    摘要: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

    摘要翻译: 延迟时间调整方法调整输入信号的延迟时间,使得输入信号的相位和输出信号的相位彼此匹配。 延迟时间调整方法包括延迟输出信号的相位,直到输入信号的相位和输出信号的相位之间的相位差成为N个周期,其中N是除零之外的整数。

    ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT
    6.
    发明申请
    ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT 审中-公开
    模拟电路单元阵列和模拟集成电路

    公开(公告)号:US20100133589A1

    公开(公告)日:2010-06-03

    申请号:US12617608

    申请日:2009-11-12

    IPC分类号: H01L25/03

    摘要: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

    摘要翻译: 模拟电路单元阵列包括排列成阵列的多个晶体管单元。 每个晶体管单元包括第一源极区域,第一沟道区域,公共漏极区域,第二沟道区域和与另一个相邻布置的第二源极区域; 以及分别形成在所述第一沟道区域和所述第二沟道区域上的第一栅极电极和第二栅极电极,并且其中所述第一栅极电极和所述第二栅极电极连接在一起使用,并且所述第一源极区域和所述第二源极 区域连接在一起使用。

    Task scheduling method in case of simultaneous transfer of compressed data and non-compressed data
    7.
    发明授权
    Task scheduling method in case of simultaneous transfer of compressed data and non-compressed data 失效
    在同时传输压缩数据和非压缩数据的情况下的任务调度方法

    公开(公告)号:US07533192B2

    公开(公告)日:2009-05-12

    申请号:US11073602

    申请日:2005-03-08

    IPC分类号: G06F3/00 G06F13/00 G06F5/00

    摘要: The invention provides a task scheduling method which can prevent overflowing of a buffer on a host system or a data encoding/decoding apparatus even when the transfer rate falls in case the compressed data and the non-compressed data are simultaneously transferred between the host system and the data encoding/decoding apparatus. In a task scheduling method, the compressed audio/video data is transferred from the buffer of the host system to an external device with a first transfer priority. The non-compressed audio/video data is transferred from the buffer to the external device with a second transfer priority lower than the first transfer priority.

    摘要翻译: 本发明提供一种任务调度方法,即使在压缩数据和非压缩数据在主机系统与主机系统之间同时传送的情况下,即使传输速率下降,也可以防止主机系统或数据编码/解码装置上的缓冲器溢出 数据编码/解码装置。 在任务调度方法中,将压缩的音频/视频数据从主机系统的缓冲器传送到具有第一传送优先级的外部设备。 非压缩音频/视频数据以比第一传送优先级低的第二传送优先级从缓冲器传送到外部设备。

    Semiconductor device and its manufacture method
    8.
    发明授权
    Semiconductor device and its manufacture method 有权
    半导体器件及其制造方法

    公开(公告)号:US07696555B2

    公开(公告)日:2010-04-13

    申请号:US11302198

    申请日:2005-12-14

    申请人: Taiji Ema

    发明人: Taiji Ema

    IPC分类号: H01L29/76

    摘要: A semiconductor device includes: a first insulating layer with a flat surface formed over a semiconductor substrate structure in which a plurality of semiconductor elements are formed; column-like conductive plugs formed to penetrate the first insulating layer in the thickness direction; elongated wall-like conductive plugs formed through the first insulating layer in the thickness direction; a second insulating layer with a flat surface formed on the first insulating layer covering the column-like conductive plugs and the wall-like conductive plugs; and first wirings having dual damascene structures. Each of the first wirings has a first portion penetrating the second insulating layer in the thickness direction and connected to at least one of the columnar conductive plugs, and a second portion formed in the second insulating layer to an intermediate depth and apparently intersects at least one of the wall-like conductive plugs when viewed above.

    摘要翻译: 半导体器件包括:形成在其上形成有多个半导体元件的半导体衬底结构上的平坦表面的第一绝缘层; 形成为在厚度方向上穿透第一绝缘层的柱状导电插塞; 在厚度方向上通过第一绝缘层形成的细长壁状导电插塞; 在覆盖柱状导电插塞和壁状导电插塞的第一绝缘层上形成有平坦表面的第二绝缘层; 以及具有双镶嵌结构的第一布线。 每个第一布线具有在厚度方向上穿透第二绝缘层的第一部分并且连接到至少一个柱状导电插塞,以及形成在第二绝缘层中的第二部分到中间深度并且明显地相交于至少一个 的壁状导电塞。

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号:US20100032745A1

    公开(公告)日:2010-02-11

    申请号:US12537913

    申请日:2009-08-07

    IPC分类号: H01L29/788 H01L21/336

    摘要: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

    摘要翻译: 半导体器件包括:存储单元晶体管,其具有浮置栅极,控制栅极,以及经由沟道区域形成在浮置栅极两侧的半导体衬底中的源极和漏极; 以及选择晶体管,其具有在所述选择栅极的两侧上形成在所述半导体衬底中的选择栅极和源极和漏极,其中所述选择晶体管的源极连接到所述存储单元晶体管的漏极, 存储单元晶体管具有N型第一杂质扩散层,比第一杂质扩散层更深的N型第二杂质扩散层和比第二杂质扩散层浅的N型第三杂质扩散层, 第二杂质扩散层的杂质浓度低于第三杂质扩散层的杂质浓度。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US07593275B2

    公开(公告)日:2009-09-22

    申请号:US12046783

    申请日:2008-03-12

    申请人: Hiroyuki Sugamoto

    发明人: Hiroyuki Sugamoto

    IPC分类号: G11C7/02

    CPC分类号: G11C7/22 G11C7/227

    摘要: According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line to be connected to the memory cell and a replica word line are connected, the semiconductor memory device comprising: a write control signal generating unit that includes logic gates coupled in multi stages for receiving an input of a replica word line activating signal generated in response to a driving signal for driving the replica word line, the write control signal generating unit generating a write control signal to determine a data write time required to write data in the memory cell based on the replica word line activating signal.

    摘要翻译: 根据一个实施例的一个方面,提供了半导体存储器件,通过读取具有等效于位线的负载的复制位线的复制单元来确定从存储器单元读取数据所需的数据读取时间 连接到存储器单元并且复制字线被连接,所述半导体存储器件包括:写入控制信号生成单元,其包括以多级耦合的逻辑门,用于接收响应于所述存储单元生成的复制字线激活信号的输入 用于驱动复制字线的驱动信号,写入控制信号产生单元产生写入控制信号,以基于复制字线激活信号确定在存储器单元中写入数据所需的数据写入时间。