公开(公告)号：US12131979B2

公开(公告)日：2024-10-29

申请号：US17648565

申请日：2022-01-21

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Luguang Wang ,  Xiaoling Wang

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L23/373 ,  H01L21/308

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/3736 ,  H01L21/3083 ,  H01L21/76802

摘要： The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, the base including a substrate and a first heat dissipation structure located in the substrate, heat conductivity of the first heat dissipation structure being higher than that of the substrate, the substrate including an upper surface and a lower surface opposite to each other, and a surface of the first heat dissipation structure being exposed on the upper surface of the substrate; a second heat dissipation structure, the second heat dissipation structure being at least located on an upper surface of the first heat dissipation structure; and a through silicon via (TSV) structure, the TSV structure penetrating through an entire thickness of the second heat dissipation structure and extending into the base, the second heat dissipation structure surrounding the TSV structure, and the first heat dissipation structure surrounding the TSV structure.

公开(公告)号：US12131953B2

公开(公告)日：2024-10-29

申请号：US17573764

申请日：2022-01-12

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Juanjuan Huang ,  Jie Bai

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/786 ,  H01L29/808

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L27/0922 ,  H01L29/78687 ,  H01L29/78696 ,  H01L29/808

摘要： A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure comprises: providing a substrate comprising a first area for forming a P-channel Metal Oxide Semiconductor (PMOS) transistor and a second area for forming an N-channel Metal Oxide Semiconductor (NMOS) transistor; forming a channel layer on the surface of the first area of the substrate; adjusting the oxidation rate of the channel layer to reduce the difference between the oxidation rate of the channel layer and the oxidation rate of the substrate; and oxidizing the surfaces of the channel layer and the second area of the substrate to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate.

公开(公告)号：US12125887B2

公开(公告)日：2024-10-22

申请号：US17455998

申请日：2021-11-22

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Fencheng Zheng

IPC分类号： H01L21/67 ,  H01L29/40

CPC分类号： H01L29/401 ,  H01L21/67144 ,  H01L21/67259

摘要： The embodiment of the present application discloses a mounting apparatus and a mounting method. The mounting apparatus comprises: a bracket; a tray movably disposed on the bracket, wherein the tray comprises the first bearing portion and the second bearing portion, the second bearing portion is disposed around the circumference of the first bearing portion and coincides with the center of gravity of the first bearing portion, a first sensor, which is disposed at the center of gravity of the first bearing portion and collects the offset of the center of gravity of the supported first upper electrode portion and the second upper electrode portion; and a driving assembly, which is connected to the tray, drives the tray to ascend and descend and drives the tray to adjust the supporting positions of the first upper electrode portion and the second upper electrode portion.

公开(公告)号：US12125874B2

公开(公告)日：2024-10-22

申请号：US17647481

申请日：2022-01-10

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kyoungyoon Baek

IPC分类号： H01L23/522 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L28/92

摘要： The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a substrate, a laminated structure, and capacitor units, and the laminated structure includes support layers; forming a first mask layer, wherein the first mask layer covers a top surface of the laminated structure; forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the laminated structure, and a projection region of the first opening on the substrate at least partially overlaps with projection regions of the capacitor units on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening, and the shielding structure covers a sidewall of the first opening.

公开(公告)号：US12125749B2

公开(公告)日：2024-10-22

申请号：US17479146

申请日：2021-09-20

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Yuanhao Gao

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/76898 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/53238

摘要： Embodiments of this application provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: a first substrate is provided; the back surface of the first substrate is etched to form a trench; a conductive layer is formed in the trench; a first conductive column that extends into the trench is formed at a back surface of the first substrate; a device layer is formed at a front surface of the first substrate, and the device layer includes a storage array and a contact structure; and a second conductive column that penetrates through the device layer and extends into the first substrate is formed; the first conductive column is electrically connected with the second conductive column through the conductive layer.

公开(公告)号：US12125704B2

公开(公告)日：2024-10-22

申请号：US17647766

申请日：2022-01-12

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Qiang Wan ,  Jun Xia ,  Kangshu Zhan ,  Penghui Xu ,  Tao Liu ,  Sen Li

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0335 ,  H01L21/0337

摘要： A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

公开(公告)号：US12122014B2

公开(公告)日：2024-10-22

申请号：US17443538

申请日：2021-07-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Jinwei Dang ,  Chin-Chung Ku ,  Lingfeng Han

IPC分类号： B24B37/34 ,  B24B37/04

CPC分类号： B24B37/34 ,  B24B37/042

摘要： The replacing tool includes a first beam, a connection mechanism, a second beam, a first hook, and a second hook. The first beam is connected to the second beam through the connection mechanism. The first hook is fixedly connected to the first beam, and a portion of the first hook is configured to be engaged into a concave end of the sponge brush. The second hook is fixedly connected to the second beam, and a portion of the second hook is arranged around a convex end of the sponge brush. The first beam and the second beam are movable relative to each other, so that the first hook is engaged with or detached from the concave end of the sponge brush and the second hook is engaged with or detached from the convex end of the sponge brush.

公开(公告)号：US12119315B2

公开(公告)日：2024-10-15

申请号：US17650851

申请日：2022-02-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chih-Wei Chang

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03622 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06548

摘要： A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

公开(公告)号：US12119286B2

公开(公告)日：2024-10-15

申请号：US17647883

申请日：2022-01-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： ChihCheng Liu

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L25/0657 ,  H01L2225/06541

摘要： A die, a memory and a method of manufacturing the die are provided. The die includes a substrate and a conductive structure, where the substrate has an interconnection structure layer, the conductive structure includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, and a coefficient of thermal expansion of the first conductive structure is smaller than that of copper.

公开(公告)号：US12119083B2

公开(公告)日：2024-10-15

申请号：US17874813

申请日：2022-07-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Shuhao Zhang ,  Ning Li

IPC分类号： G11C11/08 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  H03K3/356

CPC分类号： G11C8/08 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4096 ,  H03K3/356113

摘要： A drive circuit, a method for driving the drive circuit and a memory are provided. The drive circuit includes a word line drive circuit and a first control circuit. The word line drive circuit includes an input terminal, an output terminal and at least one N-type transistor. The word line drive circuit is configured to provide an output signal to the output terminal according to an input signal received by the input terminal. The first control circuit is configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor in the word line drive circuit, to reduce a leakage current of the at least one N-type transistor.