公开(公告)号：US08633582B2

公开(公告)日：2014-01-21

申请号：US12702482

申请日：2010-02-09

Applicant: Shu-Ming Chang ,  Cheng-Te Chou

Inventor： Shu-Ming Chang ,  Cheng-Te Chou

IPC: H01L23/48

CPC classification number: H01L23/5389 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/83855 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/03

Abstract: A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 该封装包括载体基板和其上的至少一个半导体芯片。 半导体芯片具有多个导电焊盘，其中多个第一再分配层（RDL）设置在其上并与其电连接。 单层绝缘结构覆盖载体基板和具有暴露多个第一RDL的多个开口的半导体芯片。 多个第二RDL设置在单层绝缘结构上并且电连接到多个第一RDL。 钝化层设置在单层绝缘结构上，并且多个第二RDL具有暴露多个第二RDL的多个开口。 多个导电凸块相应地设置在多个开口中以电连接到多个第二RDL。 还公开了芯片封装的制造方法。

公开(公告)号：US20120280389A1

公开(公告)日：2012-11-08

申请号：US13553331

申请日：2012-07-19

Applicant: Chien-Hung LIU ,  Cheng-Te Chou

Inventor： Chien-Hung LIU ,  Cheng-Te Chou

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.

Abstract translation: 本发明提供了一种芯片封装，包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 以及多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构，其中重掺杂区域设置在结合到半导体衬底的第一表面的载体衬底中。

公开(公告)号：US20110042804A1

公开(公告)日：2011-02-24

申请号：US12788091

申请日：2010-05-26

Applicant: Chien-Hung Liu ,  Cheng-Te Chou

Inventor： Chien-Hung Liu ,  Cheng-Te Chou

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构; 以及在重掺杂区域下面的多个导电凸块，并通过重掺杂区域电连接到导电焊盘结构。

公开(公告)号：US20110042796A1

公开(公告)日：2011-02-24

申请号：US12702482

申请日：2010-02-09

Applicant: Shu-Ming CHANG ,  Cheng-Te Chou

Inventor： Shu-Ming CHANG ,  Cheng-Te Chou

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/83855 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/03

Abstract: A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 该封装包括载体基板和其上的至少一个半导体芯片。 半导体芯片具有多个导电焊盘，其中多个第一再分配层（RDL）设置在其上并与其电连接。 单层绝缘结构覆盖载体基板和具有暴露多个第一RDL的多个开口的半导体芯片。 多个第二RDL设置在单层绝缘结构上并且电连接到多个第一RDL。 钝化层设置在单层绝缘结构上，并且多个第二RDL具有暴露多个第二RDL的多个开口。 多个导电凸块相应地设置在多个开口中以电连接到多个第二RDL。 还公开了芯片封装的制造方法。

公开(公告)号：US08748949B2

公开(公告)日：2014-06-10

申请号：US12940607

申请日：2010-11-05

Applicant: Chien-Hung Liu ,  Cheng-Te Chou

Inventor： Chien-Hung Liu ,  Cheng-Te Chou

IPC: H01L23/48 ,  H01L21/70 ,  H01L29/40

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构; 以及在重掺杂区域下面的多个导电凸块，并通过重掺杂区域电连接到导电焊盘结构。

公开(公告)号：US20110042807A1

公开(公告)日：2011-02-24

申请号：US12940607

申请日：2010-11-05

Applicant: Chien-Hung LIU ,  Cheng-Te Chou

Inventor： Chien-Hung LIU ,  Cheng-Te Chou

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

公开(公告)号：US08922026B2

公开(公告)日：2014-12-30

申请号：US13553331

申请日：2012-07-19

Applicant: Chien-Hung Liu ,  Cheng-Te Chou

Inventor： Chien-Hung Liu ,  Cheng-Te Chou

IPC: H01L23/48 ,  H01L21/00 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.

Abstract translation: 本发明提供了一种芯片封装，包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 以及多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构，其中重掺杂区域设置在结合到半导体衬底的第一表面的载体衬底中。

公开(公告)号：US08431950B2

公开(公告)日：2013-04-30

申请号：US12471255

申请日：2009-05-22

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract translation: 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。

公开(公告)号：US08497534B2

公开(公告)日：2013-07-30

申请号：US12788091

申请日：2010-05-26

Applicant: Chien-Hung Liu ,  Cheng-Te Chou

Inventor： Chien-Hung Liu ,  Cheng-Te Chou

IPC: H01L23/48 ,  H01L23/02 ,  H01L21/00

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构; 以及在重掺杂区域下面的多个导电凸块，并通过重掺杂区域电连接到导电焊盘结构。

公开(公告)号：US20090289273A1

公开(公告)日：2009-11-26

申请号：US12471255

申请日：2009-05-22

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC: H01L33/00

CPC classification number: H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract translation: 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。