公开(公告)号：US20140076392A1

公开(公告)日：2014-03-20

申请号：US13621879

申请日：2012-09-18

申请人： Chih Ching LIN ,  Yong-Ping CHAN ,  Wei-Chun HSU ,  Chen-Yun WANG

发明人： Chih Ching LIN ,  Yong-Ping CHAN ,  Wei-Chun HSU ,  Chen-Yun WANG

IPC分类号： H01L31/0216 ,  H01L31/18

CPC分类号： H01L31/022466 ,  H01L31/022483 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/073 ,  H01L31/0749 ,  H01L31/18 ,  Y02E10/541 ,  Y02E10/543 ,  Y02P70/521

摘要： A thin film solar cell and process for forming the same. The solar cell includes a bottom electrode layer, semiconductor light absorbing layer, and a TCO top electrode layer. In one embodiment, a TCO seed layer is formed between the top electrode and absorber layers to improve adhesion of the top electrode layer to the absorber layer. In one embodiment, the seed layer is formed at a lower temperature than the TCO top electrode layer and has a different microstructure.

摘要翻译： 薄膜太阳能电池及其形成方法。 太阳能电池包括底电极层，半导体光吸收层和TCO顶电极层。 在一个实施例中，在顶部电极和吸收层之间形成TCO种子层，以改善顶部电极层与吸收层的粘附。 在一个实施方案中，种子层形成在比TCO顶部电极层低的温度下，具有不同的微结构。

公开(公告)号：US08640074B2

公开(公告)日：2014-01-28

申请号：US13298315

申请日：2011-11-17

申请人： Shen-Yu Huang ,  Chih-Ching Lin

发明人： Shen-Yu Huang ,  Chih-Ching Lin

IPC分类号： G06F17/50 ,  G01R27/16 ,  G01R31/20

CPC分类号： H01L27/0207 ,  H01L23/5223 ,  H01L23/5286 ,  H01L28/20 ,  H01L2924/0002 ,  H03K19/00346 ,  H01L2924/00

摘要： A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.

摘要翻译： 数字电路块包括第一至第四导电段，数字逻辑，第一和第二导电层以及电介质层。 第一和第二导电段分别耦合到第一和第二电源电压。 数字逻辑和电介质层位于第一和第二导电段之间。 第三导电段包括电连接到第一导电段的第一端，不电连接到第二导电段的第二端和位于第一导电层的第一部分。 第四导电段包括电连接到第二导电段的第一端，不电连接到第一导电段的第二端和位于第二导电层的第二部分。 第一和第二部分和电介质层形成第一电容元件以减小第一和第二电源电压之间的电源电压降。

公开(公告)号：US20120302065A1

公开(公告)日：2012-11-29

申请号：US13116164

申请日：2011-05-26

申请人： Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

发明人： Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

IPC分类号： H01L21/3065 ,  C23F1/08

CPC分类号： H01J37/32577 ,  H01J37/32082 ,  H01J37/32146 ,  H01J37/32532 ,  H01J2237/334 ,  H01J2237/3347 ,  H01L21/31116

摘要： The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (Toff).

摘要翻译： 脉冲等离子体蚀刻方法及其制造方法本发明涉及一种脉冲等离子体蚀刻方法及其制造方法。 脉冲等离子体蚀刻装置包括容器，上电极板，下电极板，气体源，第一超高频RF电源，偏置RF电源和脉冲模块。 当脉冲模块在上电极板和下电极板之间提供超高频电压时，超高频电压被切换到关闭状态，并且大量电子通过等离子体并到达衬底以中和 在离开状态持续时间内的正离子（Toff）。

公开(公告)号：US20120302062A1

公开(公告)日：2012-11-29

申请号：US13116432

申请日：2011-05-26

申请人： Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

发明人： Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

IPC分类号： H01L21/28

CPC分类号： H01L21/0273 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76898

摘要： A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.

摘要翻译： 在半导体器件中通孔形成的方法包括以下步骤：提供具有限定通孔开口的光致抗蚀剂图案的光致抗蚀剂，其中包含热交联材料的光致抗蚀剂设置在结构层上; 将结构层干蚀刻穿过开口的第一深度; 烘烤热交联材料以减少开口; 并且通过所述减小的开口将所述结构层干蚀刻到第二深度，其中所述第二深度大于所述第一深度。

公开(公告)号：US20070099125A1

公开(公告)日：2007-05-03

申请号：US11564238

申请日：2006-11-28

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： G03C5/00

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US08772928B2

公开(公告)日：2014-07-08

申请号：US13205648

申请日：2011-08-09

申请人： Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

发明人： Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/5223 ,  H01L24/05

摘要： An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.

摘要翻译： 集成电路芯片包括位于半导体衬底上的最顶层金属层中的电源/接地互连网络，以及至少在电力/接地互连网络上/之上的凸块焊盘。 电源/接地网状互连网络包括连接到凸块焊盘并沿着第一方向延伸的第一电源/接地线，以及连接到凸块焊盘并沿第二方向延伸的连接部分。

公开(公告)号：US07949988B2

公开(公告)日：2011-05-24

申请号：US12060298

申请日：2008-04-01

申请人： Tung-Kai Tsai ,  Chih-Ching Lin

发明人： Tung-Kai Tsai ,  Chih-Ching Lin

IPC分类号： G06F17/50 ,  G06F15/04 ,  H03K19/013 ,  H03K19/00 ,  H03K19/094

CPC分类号： G06F17/5068 ,  G06F2217/72 ,  H01L27/0207 ,  H01L27/11807

摘要： A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

摘要翻译： 提供了一种布局电路，包括标准单元，备用单元，组合连接单元和普通填充单元。 标准单元被布置并布置在布局区域上。 在布局区域中添加备用单元，并在稍后添加或更改功能时提供替换其中一个标准单元。 组合的领带单元被添加在布局区域上。 正常填充单元被添加到布局区域的其余部分。 组合式连接单元包括连接高电路，连接低电路和电容电路。 一些标准单元设置在至少一个组合的连接单元附近，以避免组合连接单元与替换的标准单元之间的路由拥塞。 还提供了电路布局方法。

公开(公告)号：US07678692B2

公开(公告)日：2010-03-16

申请号：US11564238

申请日：2006-11-28

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US20050202671A1

公开(公告)日：2005-09-15

申请号：US10908824

申请日：2005-05-27

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC分类号： H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/768

CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

摘要翻译： 提供一种用于制造互连的方法。 该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。 由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。

公开(公告)号：US20050048749A1

公开(公告)日：2005-03-03

申请号：US10708848

申请日：2004-03-29

申请人： TSE-YAO HUANG ,  YI-NAN CHEN ,  CHIH-CHING LIN

发明人： TSE-YAO HUANG ,  YI-NAN CHEN ,  CHIH-CHING LIN

IPC分类号： H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/768

CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

摘要翻译： 提供一种用于制造互连的方法。 该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。 由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。