公开(公告)号：US08969108B2

公开(公告)日：2015-03-03

申请号：US13881723

申请日：2011-02-10

申请人： Deyuan Xiao ,  Richard Rugin Chang

发明人： Deyuan Xiao ,  Richard Rugin Chang

IPC分类号： H01L29/06 ,  H01L33/64 ,  H01L33/00 ,  H01L21/20

CPC分类号： H01L33/385 ,  H01L21/2007 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/62 ,  H01L33/641

摘要： A light emitting diode (LED) and a forming method thereof are provided. The method for forming the LED includes: providing a semiconductor substrate (20) and a sapphire substrate (30) respectively, wherein a first bonding layer (21) is formed on the silicon substrate (20), and a sacrificial layer (32), an LED die (33) and a second bonding layer (35) are formed in turn on the sapphire substrate (30); bonding the first bonding layer (21) and the second bonding layer (35); removing the sacrificial layer (32) and lifting off the sapphire substrate (30). The method increases the effective lighting area of the LED, improves heat radiation, and enhances lighting efficiency.

摘要翻译： 提供一种发光二极管（LED）及其形成方法。 形成LED的方法包括：分别提供半导体衬底（20）和蓝宝石衬底（30），其中在硅衬底（20）上形成第一接合层（21）和牺牲层（32）， 依次在蓝宝石衬底（30）上形成LED管芯（33）和第二接合层（35）; 接合第一接合层（21）和第二接合层（35）; 去除牺牲层（32）并提起蓝宝石衬底（30）。 该方法增加了LED的有效照明面积，改善了散热，提高了照明效率。

公开(公告)号：US08833431B2

公开(公告)日：2014-09-16

申请号：US13059634

申请日：2010-12-30

申请人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Qing Rao

发明人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Qing Rao

IPC分类号： B22D17/00

CPC分类号： C22C21/00 ,  B22D17/00 ,  C22C1/026 ,  C22C1/1036 ,  C22C26/00 ,  F21V29/85 ,  H01L23/3733 ,  H01L23/3736 ,  H01L33/641 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2933/0075 ,  H01L2924/00

摘要： The present invention discloses an aluminum alloy material, which is made of raw material of aluminum alloy. The raw material of aluminum alloy consists of the following constituents by percentage of weight: graphene: 0.1%˜1%, carbon nano tube: 1%˜5%, the rest being Al. The aluminum alloy material of the present invention has a good performance of heat dissipation, the thermal conductivity is higher than 200 W/m. Meanwhile, the present invention further provides a method of manufacturing aluminum alloy backboard, in which method, the raw material of aluminum alloy is heated and melted in a heating furnace, afterwards, the raw material of aluminum alloy after melting is formed into an aluminum alloy backboard by die-casting, in this way, the utilization rate of material is increased and the manufacturing cost of the backboard is reduced.

摘要翻译： 本发明公开了一种由铝合金原料制成的铝合金材料。 铝合金原料由以下重量百分比组成：石墨烯：0.1％〜1％，碳纳米管：1％〜5％，其余为Al。 本发明的铝合金材料具有良好的散热性能，导热系数高于200W / m。 同时，本发明还提供一种制造铝合金背板的方法，其中将铝合金原料在加热炉中加热熔化，之后将熔融后的铝合金原料形成为铝合金 通过压铸，通过这种方式，材料的利用率提高，背板的制造成本降低。

公开(公告)号：US08264042B2

公开(公告)日：2012-09-11

申请号：US12810574

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

摘要： A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

摘要翻译： 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。

公开(公告)号：US08233312B2

公开(公告)日：2012-07-31

申请号：US12934745

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/24

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的第一N型半导体区域，设置在第一N型半导体区域上的P型半导体区域，设置在P型半导体区域上的栅极区域和围绕P型半导体区域的电隔离区域 型半导体区域和N型半导体区域。 二极管作为存储节点。 通过带之间的隧道效应，孔被聚集在浮体中，其被定义为第一储存状态; 通过PN结的正向偏压，空穴从浮体发射出来，或者电子被注入浮动体，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US08217471B2

公开(公告)日：2012-07-10

申请号：US12650494

申请日：2009-12-30

申请人： Deyuan Xiao

发明人： Deyuan Xiao

IPC分类号： H01L29/772

CPC分类号： H01L29/0847 ,  H01L21/823814 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion. The FET also includes a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type. A first drain portion is positioned within second portion and characterized by the second conductivity type and a first doping concentration. A second drain portion is positioned within the second portion and is characterized by the second conductivity type and a second doping concentration, the second doping concentration being different from the first doping concentration.

摘要翻译： 金属氧化物半导体场效应晶体管的系统和方法。 在具体实施例中，本发明提供一种场效应晶体管（FET），其包括基板材料，所述基板材料的特征在于第一导电类型，所述基板材料包括第一部分，第二部分和第三部分， 第三部分位于第一部分和第二部分之间。 FET还包括位于第一部分内的源极部分，源极部分由第二导电类型表征，第二导电类型与第一导电类型相反。 第一漏极部分位于第二部分内，其特征在于第二导电类型和第一掺杂浓度。 第二漏极部分位于第二部分内，其特征在于第二导电类型和第二掺杂浓度，第二掺杂浓度不同于第一掺杂浓度。

公开(公告)号：US20110254100A1

公开(公告)日：2011-10-20

申请号：US12810648

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented.

摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在积累模式中，电流流过整个跑道状通道。 所公开的器件具有高的载流子迁移率，高的器件驱动电流，并且保持器件的电气完整性。 同时，防止了多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US08704227B2

公开(公告)日：2014-04-22

申请号：US13059399

申请日：2010-12-30

申请人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Chijen Hsu

发明人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Chijen Hsu

IPC分类号： H01L29/04

CPC分类号： H01L33/24 ,  H01L33/007 ,  H01L33/12 ,  H01L33/20

摘要： The present invention discloses an LED and its fabrication method. The LED comprises: a sapphire substrate; an epitaxial layer, an active layer and a capping layer arranged on the sapphire substrate in sequence; wherein a plurality of cone-shaped structures are formed on the surface of the sapphire substrate close to the epitaxial layer. The cone-shaped structures can increase the light reflected by the sapphire substrate, raising the external quantum efficiency of the LED, thus increasing the light utilization rate of the LED. Furthermore, the formation of a plurality of cone-shaped structures can improve the lattice matching between the sapphire substrate and other films, reducing the crystal defects in the film formed on the sapphire substrate, increasing the internal quantum efficiency of the LED.

摘要翻译： 本发明公开了一种LED及其制造方法。 LED包括：蓝宝石衬底; 一个外延层，一个有源层和一个盖层，依次布置在蓝宝石衬底上; 其中在蓝宝石衬底的靠近外延层的表面上形成多个锥形结构。 锥形结构可以增加由蓝宝石衬底反射的光，提高LED的外部量子效率，从而提高LED的光利用率。 此外，多个锥形结构的形成可以改善蓝宝石衬底和其他膜之间的晶格匹配，减少在蓝宝石衬底上形成的膜中的晶体缺陷，增加LED的内部量子效率。

公开(公告)号：US20130214245A1

公开(公告)日：2013-08-22

申请号：US13059631

申请日：2010-12-30

申请人： Richard Rugin Chang ,  Deyuan Xiao

发明人： Richard Rugin Chang ,  Deyuan Xiao

IPC分类号： H01L33/58 ,  H01L33/06

CPC分类号： H01L33/58 ,  H01L33/06 ,  H01L33/20 ,  H01L2933/0091

摘要： The present invention discloses an LED and its fabrication method. The LED comprises: a substrate; an epitaxial layer, an active layer and a capping layer arranged on the substrate in sequence; wherein a plurality of microlens structures arc formed on the surface of the substrate away from the epitaxial layer, and a plurality of cams are formed on the surfaces of the microlens structures. When the light emitted from the active layer passes through the surfaces of the microlens structures or the surfaces of the cams, the incident angle is always smaller than the critical angle of total reflection, thus preventing total reflection and making sure that most of the light pass through the surfaces of the microlens structures and the cams, in this way improving external quantum efficiency of the LED, avoiding the rise of the internal temperature of the LED and improving the performance of the LED.

摘要翻译： 本发明公开了一种LED及其制造方法。 LED包括：基板; 一个外延层，一个活性层和一个覆盖层，依次排列在基片上; 其中在所述衬底的表面上形成多个微透镜结构，远离所述外延层，并且在所述微透镜结构的表面上形成多个凸轮。 当从有源层发射的光通过微透镜结构或凸轮表面时，入射角度总是小于全反射的临界角，从而防止全反射并确保大部分光通过 通过微透镜结构和凸轮的表面，以这种方式提高LED的外部量子效率，避免LED的内部温度升高并提高LED的性能。

公开(公告)号：US08513727B2

公开(公告)日：2013-08-20

申请号：US12892879

申请日：2010-09-28

申请人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

发明人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

摘要： Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.

摘要翻译： 具有低关断状态泄漏电流和优异的数据保持时间特性的非易失性存储器件。 本发明提供了一种包括堆叠的栅极鳍效应晶体管非易失性存储器结构，其包括第一导电类型的绝缘体上硅衬底和从绝缘体的上表面突出的鳍状有源区。 该结构还包括形成在翅片有源区上的隧道氧化物层和设置在隧道氧化物层和绝缘体的上表面上的第一栅电极。 另外，该结构包括形成在第一栅电极上的氧化物/氮化物/氧化物（ONO）复合层，形成在ONO复合层上的第二栅极，并且被图案化以限定ONO复合层的预定区域。 该结构还包括形成在第二栅电极的侧壁上的介质间隔物和形成在第二栅电极两侧的鳍有源区中的源/漏区。

公开(公告)号：US08409962B2

公开(公告)日：2013-04-02

申请号：US12937264

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang

发明人： Deyuan Xiao ,  Xiaolu Huang

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： present invention discloses a manufacturing method for a copper interconnection structure with MIM capacitor. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor.

摘要翻译： 本发明公开了一种具有MIM电容器的铜互连结构的制造方法。 该方法首先在铜互连结构中形成铜导电图案，并与铜导电图案连接的铜通孔螺栓; 蚀刻围绕铜通孔螺栓的绝缘层，并沉积蚀刻停止层，以暴露铜通孔螺栓和铜导电图案的顶表面的一部分的顶表面和侧表面; 在所获得的结构上沉积介电层，并在所获得的结构的凹陷区域中填充保护材料; 蚀刻用于接收其它铜导电图案的沟槽; 取下保护材料; 在凹陷区域镀铜，并在沟槽中镀铜，以获得具有MIM电容器的铜互连结构。