摘要:
Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.
摘要:
Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.
摘要:
An apparatus and method for a wire-bond die-up area array package is described. The package includes an integrated circuit (IC) die, a substrate, and a thermally conducting body. A bottom surface of the IC die is exposed through an opening in a central region of the substrate. The die is mounted to the thermally conducting body. A bottom surface of the thermally conducting body is configured to be connected to a circuit board, such as a PWB, when the package is mounted to the circuit board. The bottom surface of the thermally conducting body may be connected directly to the circuit board, or may be coupled to the circuit board via solder balls or other mechanism. One or more wirebonds are used to electrically connect the die to a top surface of the substrate. A mold compound encapsulates the die, the wirebonds, and at least a portion of the top surface of the substrate, and fills a gap between peripheral edges of the IC die and inner walls of the substrate central window opening. A matrix of solder balls is attached to a bottom surface of the substrate.
摘要:
Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.
摘要:
A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.
摘要:
An integrated circuit (IC) package has a package member having a first surface and a second surface opposite the first surface. A first plurality of contact members is physically and electrically fixed to the second surface. An interposer substrate having a second plurality of contact members on one surface thereof which make physical and electrical contact with respective ones of the first plurality of contact members. The interposer substrate is configured to have at least one circuit member mounted to a second surface thereof opposite the one surface thereof.
摘要:
Methods and apparatus for improved electrical, mechanical and thermal performance of stacked IC packages are described. An IC package comprises a substrate, a first die, a second die, and an interposer with an opening in a first surface of the interposer configured to accommodate the first die. The first IC die is attached a first surface of the substrate. The interposer is mounted on the first surface of the substrate such that the first IC die is placed within the opening in the interposer. The second die is mounted on a second surface of the interposer. Wire bonds couple bond pads on the first surfaces of IC die are coupled to the first surface of the substrate. A mold compound encapsulates the first IC die, the second IC die, the interposer and the wire bonds.
摘要:
Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes first and second caps defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. Planar rim portions of the first and second caps that surround the cavity are coupled to the leadframe. The first and second caps and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.
摘要:
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface. In another aspect, wire bond openings in the stiffener are bridged by one or more studs.
摘要:
A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of the IC die. The package also includes a thermally conductive interposer which is thermally coupled to the IC die at the contact pads. In another aspect, an underfill material fills a space between the IC die and the interposer. The interposer may also be electrically coupled to the IC die. In an aspect, the interposer and the IC die are coupled through thermal interconnects or “nodules.”