公开(公告)号：US20110285021A1

公开(公告)日：2011-11-24

申请号：US13191090

申请日：2011-07-26

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

IPC分类号： H01L23/52 ,  B82Y99/00

CPC分类号： H01L21/76826 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

摘要翻译： 提供了包括具有约3.0或更小介电常数的介电材料的互连结构。 该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。 电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。 贵金属盖直接位于至少一个导电材料的上表面上。 由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物 沉积形式在该疏水电介质表面上。

公开(公告)号：US07863083B2

公开(公告)日：2011-01-04

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/266 ,  H01L21/425

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US07749802B2

公开(公告)日：2010-07-06

申请号：US11621365

申请日：2007-01-09

申请人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

发明人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

IPC分类号： H01L21/00 ,  H01L21/82 ,  H01L21/20

CPC分类号： C23C16/30 ,  H01L21/28556 ,  H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1683 ,  Y10T428/249994

摘要： A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.

摘要翻译： 提供了一种用于沉积包括锗（Ge）和锑（Sb）在内的材料的化学气相沉积（CVD）方法，其在一些实施例中具有填充高纵横比开口的能力。 本发明的CVD方法允许在宽范围的值范围内控制GeSb化学计量，并且本发明的方法在低于400℃的衬底温度下进行，这使得本发明的方法与现有的互连工艺和材料兼容 。 除了上述之外，本发明的方法是非选择性CVD工艺，这意味着GeSb材料在绝缘和非绝缘材料上同样良好地沉积。

公开(公告)号：US20100009164A1

公开(公告)日：2010-01-14

申请号：US12540923

申请日：2009-08-13

申请人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

发明人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

IPC分类号： B32B3/26

CPC分类号： C23C16/30 ,  H01L21/28556 ,  H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1683 ,  Y10T428/249994

摘要： A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.

摘要翻译： 提供了一种用于沉积包括锗（Ge）和锑（Sb）在内的材料的化学气相沉积（CVD）方法，其在一些实施例中具有填充高纵横比开口的能力。本发明的CVD方法允许控制 在宽范围的值范围内的GeSb化学计量和本发明的方法在低于400℃的衬底温度下进行，这使得本发明的方法与现有的互连工艺和材料相兼容。 除了上述之外，本发明的方法是非选择性CVD工艺，这意味着GeSb材料在绝缘和非绝缘材料上同样良好地沉积。

公开(公告)号：US20080293259A1

公开(公告)日：2008-11-27

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

IPC分类号： H01L21/263

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有 约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

公开(公告)号：US20080166586A1

公开(公告)日：2008-07-10

申请号：US11621389

申请日：2007-01-09

申请人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

IPC分类号： H01L29/12 ,  C23C16/00

CPC分类号： C23C16/04 ,  C23C16/30 ,  Y10T428/12528

摘要： A chemical vapor deposition (CVD) method for selectively depositing GeSb materials onto a surface of a substrate is provided in which a metal that is capable of forming an eutectic alloy with germanium is used to catalyze the growth of the GeSb materials. A structure is also provided that includes a GeSb material located on preselected regions of a substrate. In accordance with the present invention, the GeSb material is sandwiched between a lower metal layer used to catalyze the growth of the GeSb and an upper surface metal layer that forms during the growth of the GeSb material.

摘要翻译： 提供了一种用于选择性地将GeSb材料沉积到衬底表面上的化学气相沉积（CVD）方法，其中能够与锗形成共晶合金的金属用于催化GeSb材料的生长。 还提供了一种结构，其包括位于基底的预选区域上的GeSb材料。 根据本发明，GeSb材料夹在用于催化GeSb生长的下金属层和GeSb材料生长期间形成的上表面金属层之间。

公开(公告)号：US06989321B2

公开(公告)日：2006-01-24

申请号：US10673908

申请日：2003-09-30

申请人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert J Leusink ,  Fenton R McFeely ,  Sandra G. Malhotra

发明人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert J Leusink ,  Fenton R McFeely ,  Sandra G. Malhotra

IPC分类号： H01L21/20 ,  H01L21/44

CPC分类号： C23C16/16 ,  H01L21/28556

摘要： A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.

摘要翻译： 通过热化学气相沉积（TCVD）方法在金属层上沉积金属层的方法包括在处理室中引入含有羰基金属前驱体的工艺气体并在基底上沉积金属层。 TCVD工艺利用在衬底上方的处理区域中的气态物质的短暂停留时间以形成低电阻率金属层。 在本发明的一个实施方案中，羰基金属前体可以选自W（CO）6，Ni（CO）4，Mo（CO） CO 2，CO 2，CO 2，CO 2，CO 2，CO 2，CO 2， Re（CO）10，Cr（CO）6和Ru 3（CO）3， 12个前体。 在本发明的另一个实施例中，提供了一种通过利用小于约120毫秒的停留时间在低于约500℃的衬底温度下沉积低电阻W层的方法。

公开(公告)号：US06448131B1

公开(公告)日：2002-09-10

申请号：US09929182

申请日：2001-08-14

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  Y10S438/964

摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

公开(公告)号：US20120208362A1

公开(公告)日：2012-08-16

申请号：US13453508

申请日：2012-04-23

申请人： Chih-Chao Yang ,  Fenton R. McFeely

发明人： Chih-Chao Yang ,  Fenton R. McFeely

IPC分类号： H01L21/768

CPC分类号： H01L21/02362 ,  H01L21/743 ,  H01L21/76841 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.

摘要翻译： 提供了一种高纵横比金属化结构，其中含贵金属的材料至少位于位于电介质材料中的接触开口的下部内，并且与位于电介质材料的上表面上的金属半导体合金直接接触 至少一个半导体器件的材料堆叠。 在一个实施方案中，含贵金属的材料是位于接触开口的下部区域内的插塞，并且接触开口的上部区域包括含导电金属的材料。 含有导电性金属的材料通过U形扩散阻挡层的底壁部与贵金属材料的塞分离。 在另一个实施方案中，含贵金属的材料存在于整个接触开口处。

公开(公告)号：US08242030B2

公开(公告)日：2012-08-14

申请号：US12566870

申请日：2009-09-25

申请人： James B. Hannon ,  Fenton R. McFeely ,  Satoshi Oida ,  John J. Yurkas

发明人： James B. Hannon ,  Fenton R. McFeely ,  Satoshi Oida ,  John J. Yurkas

IPC分类号： H01L21/461 ,  H01L21/31

CPC分类号： H01L29/16

摘要： A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer.

摘要翻译： 电活化具有形成在碳化硅层上的一个或多个石墨烯层的结构的方法包括对该结构进行氧化处理，以形成设置在碳化硅层和一个或多个石墨烯的最底部之间的氧化硅层 从而电激活最底层的石墨烯层。