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59 条记录 (耗时 0.036 秒)

    Low-pressure deposition of metal layers from metal-carbonyl precursors
    1.
    发明授权
    Low-pressure deposition of metal layers from metal-carbonyl precursors 有权
    金属 - 羰基前驱体金属层的低压沉积

    公开(公告)号：US06989321B2

    公开(公告)日：2006-01-24

    申请号：US10673908

    申请日：2003-09-30

    申请人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert J Leusink ,  Fenton R McFeely ,  Sandra G. Malhotra

    发明人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert J Leusink ,  Fenton R McFeely ,  Sandra G. Malhotra

    IPC分类号： H01L21/20 ,  H01L21/44

    CPC分类号： C23C16/16 ,  H01L21/28556

    摘要： A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.

    摘要翻译： 通过热化学气相沉积（TCVD）方法在金属层上沉积金属层的方法包括在处理室中引入含有羰基金属前驱体的工艺气体并在基底上沉积金属层。 TCVD工艺利用在衬底上方的处理区域中的气态物质的短暂停留时间以形成低电阻率金属层。 在本发明的一个实施方案中，羰基金属前体可以选自W（CO）6，Ni（CO）4，Mo（CO） CO 2，CO 2，CO 2，CO 2，CO 2，CO 2，CO 2， Re（CO）10，Cr（CO）6和Ru 3（CO）3， 12个前体。 在本发明的另一个实施例中，提供了一种通过利用小于约120毫秒的停留时间在低于约500℃的衬底温度下沉积低电阻W层的方法。

    Leakage reduction in DRAM MIM capacitors
    7.
    发明申请
    Leakage reduction in DRAM MIM capacitors 有权

    公开(公告)号：US20140080282A1

    公开(公告)日：2014-03-20

    申请号：US13621910

    申请日：2012-09-18

    申请人： Tony P. Chiang ,  Wim Y. Deweerd ,  Sandra G. Malhotra

    发明人： Tony P. Chiang ,  Wim Y. Deweerd ,  Sandra G. Malhotra

    IPC分类号： H01L21/02

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
    8.
    发明授权
    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
    在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层

    公开(公告)号：US08193090B2

    公开(公告)日：2012-06-05

    申请号：US13192777

    申请日：2011-07-28

    申请人： David E. Lazovsky ,  Sandra G. Malhotra ,  Thomas R. Boussie

    发明人： David E. Lazovsky ,  Sandra G. Malhotra ,  Thomas R. Boussie

    IPC分类号： H01L21/44

    CPC分类号： H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

    摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

    摘要翻译： 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一情况下（特别是在后者中），可以随后去除在电介质区域上形成的覆盖层材料，从而确保覆盖层材料仅在导电区域上形成。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由导电材料（例如，钴合金，镍合金，钨，钽，氮化钽），半导体材料或电绝缘材料形成，并且可以使用任何适当的工艺形成，包括 常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积。

    STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS
    9.
    发明申请
    STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
    形成电沉积联系的结构和方法

    公开(公告)号：US20090014878A1

    公开(公告)日：2009-01-15

    申请号：US12130381

    申请日：2008-05-30

    申请人： Cyril Cabral, JR. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

    发明人： Cyril Cabral, JR. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

    摘要翻译： 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

    RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS
    10.
    发明申请
    RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS 有权
    电阻开关非易失性存储器元件

    公开(公告)号：US20080278990A1

    公开(公告)日：2008-11-13

    申请号：US12114667

    申请日：2008-05-02

    申请人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

    发明人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

    IPC分类号： G11C11/00 ,  H01L21/16

    CPC分类号： H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

    摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

    摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。