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公开(公告)号:US07435618B2
公开(公告)日:2008-10-14
申请号:US11635034
申请日:2006-12-07
申请人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号: H01L21/00 , H01L21/44 , H01L21/4763
CPC分类号: H05K3/4007 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2924/0002 , H05K1/113 , H05K3/0035 , H05K3/007 , H05K3/108 , H05K3/243 , H05K3/28 , H05K3/4682 , H05K2201/09436 , H05K2201/09563 , H05K2201/096 , H05K2203/0152 , H05K2203/0376 , H01L2924/00
摘要: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.
摘要翻译: 公开了一种无芯封装基板的制造方法。 该方法可以制造无芯封装衬底,其包括:至少具有第一焊料掩模和第二焊料掩模的堆积结构,其中在第一和第二焊料掩模中形成多个开口以暴露出 建筑结构; 以及形成在导电焊盘上的多个焊料凸块以及焊料层。 因此,本发明可以生产具有高密度电路布局,较少制造步骤和小尺寸的无芯封装衬底。
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公开(公告)号:US07906850B2
公开(公告)日:2011-03-15
申请号:US11588911
申请日:2006-10-27
申请人: Shing-Ru Wang , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Shing-Ru Wang , Hsien-Shou Wang , Shih-Ping Hsu
CPC分类号: H01L23/5389 , H01L24/19 , H01L24/24 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/92244 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517
摘要: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.
摘要翻译: 提出了一种电路板结构及其制造方法。 该结构包括具有多个开口的绝缘保护层,其中形成导电通孔;形成在绝缘保护层的表面上并电连接到绝缘保护层的开口中的导电通孔的图案化电路层,以及 电介质层,其形成在绝缘保护层上和图案化电路层的表面上,其中在电介质层中形成多个开口,从而露出图案化电路层的部分。 因此,本发明可以减小电路板的厚度,减小封装尺寸,提高产品性能,并符合朝向较小型电子器件的发展趋势。
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公开(公告)号:US07867888B2
公开(公告)日:2011-01-11
申请号:US11808028
申请日:2007-06-06
申请人: Hsien-Shou Wang
发明人: Hsien-Shou Wang
IPC分类号: H01L23/532 , H01L21/44
CPC分类号: H05K3/4007 , H01L21/6835 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/3011 , H05K3/007 , H05K3/107 , H05K3/108 , H05K3/243 , H05K3/28 , H05K3/4644 , H05K2201/0367 , H05K2201/0376 , H05K2203/0152 , H05K2203/1572 , H01L2924/00
摘要: The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are formed in the first surface, the circuit layer is formed on the first surface and in the vias to electrically connect to another circuit layer disposed under the dielectric layer; a metal layer embedded in the exposed second surface of the circuit build-up structure without protruding the exposed second surface and connected to the circuit layer; and two solder masks disposed on the exposed first surface and the exposed second surface of the circuit build-up structure, wherein the solder masks have plural openings to separately expose part of the circuit layer and the metal layer functioning as conductive pads.
摘要翻译: 本发明提供了一种倒装芯片封装基板和一种用于制造倒装芯片封装基板的方法,该封装基板包括至少包括介电层和至少电路层的电路组合结构,其中每个电介质层包括第一 表面和第二表面,在第一表面中形成多个通孔,电路层形成在第一表面和通孔中,以电连接到设置在电介质层下方的另一个电路层; 嵌入在电路堆积结构的暴露的第二表面中的金属层,而不突出暴露的第二表面并连接到电路层; 以及设置在暴露的第一表面和电路堆积结构的暴露的第二表面上的两个焊接掩模,其中焊料掩模具有多个开口以分别暴露电路层的一部分和用作导电焊盘的金属层。
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公开(公告)号:US20070249155A1
公开(公告)日:2007-10-25
申请号:US11635034
申请日:2006-12-07
申请人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号: H01L21/4763
CPC分类号: H05K3/4007 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2924/0002 , H05K1/113 , H05K3/0035 , H05K3/007 , H05K3/108 , H05K3/243 , H05K3/28 , H05K3/4682 , H05K2201/09436 , H05K2201/09563 , H05K2201/096 , H05K2203/0152 , H05K2203/0376 , H01L2924/00
摘要: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.
摘要翻译: 公开了一种无芯封装基板的制造方法。 该方法可以制造无芯封装衬底,其包括:至少具有第一焊料掩模和第二焊料掩模的堆积结构,其中在第一和第二焊料掩模中形成多个开口以暴露出 建筑结构; 以及形成在导电焊盘上的多个焊料凸块以及焊料层。 因此,本发明可以生产具有高密度电路布局,较少制造步骤和小尺寸的无芯封装衬底。
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公开(公告)号:US20110154664A1
公开(公告)日:2011-06-30
申请号:US13046441
申请日:2011-03-11
申请人: Shing-Ru Wang , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Shing-Ru Wang , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号: H05K3/10
CPC分类号: H01L23/5389 , H01L24/19 , H01L24/24 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/92244 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517
摘要: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.
摘要翻译: 提出了一种电路板结构及其制造方法。 该结构包括具有多个开口的绝缘保护层,其中形成导电通孔;形成在绝缘保护层的表面上并电连接到绝缘保护层的开口中的导电通孔的图案化电路层,以及 电介质层,其形成在绝缘保护层上和图案化电路层的表面上,其中在电介质层中形成多个开口,从而露出图案化电路层的部分。 因此,本发明可以减小电路板的厚度,减小封装尺寸,提高产品性能,并符合朝向较小型电子器件的发展趋势。
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公开(公告)号:US20080122079A1
公开(公告)日:2008-05-29
申请号:US11620795
申请日:2007-01-08
申请人: Bo-Wei Chen , Hsien-Shou Wang
发明人: Bo-Wei Chen , Hsien-Shou Wang
CPC分类号: H01L21/563 , H01L21/6835 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2221/68345 , H01L2224/16 , H01L2224/45144 , H01L2224/48227 , H01L2224/48235 , H01L2224/48644 , H01L2224/48664 , H01L2224/48666 , H01L2224/73203 , H01L2224/85444 , H01L2224/85464 , H01L2224/85466 , H01L2225/0651 , H01L2225/06517 , H01L2225/06568 , H01L2225/06582 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H05K3/205 , H05K3/284 , H05K3/4007 , H05K2201/0367 , H05K2201/09481 , H05K2203/0376 , H05K2203/0384 , H05K2203/0733 , H01L2924/00 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
摘要: The package substrate of the present invention comprises a carrying board, bump pads, wire bonding pads, a solder mask, metallic bumps, and a metallic protective layer. The solder pads and the wire bonding pads are disposed on the surface of the carrying board. The solder mask is patterned to expose bump pads, wire bonding pads, and part of the surface of the substrate on the periphery of the wire bonding pads. The metallic bumps are disposed on the surface of the bump pads and extend to the surface of the solder mask. The metallic protective layer is disposed on the surfaces of the metallic bumps and the wire bonding pads. Besides, a method for manufacturing this package substrate, a semiconductor package structure comprising this package substrate, and a manufacturing method thereof are disclosed. Therefore, the manufacturing process of the package substrate is simple, and the package substrate is slim.
摘要翻译: 本发明的封装基板包括承载板,凸块,引线焊盘,焊接掩模,金属凸块和金属保护层。 焊盘和引线接合焊盘设置在承载板的表面上。 图案化焊料掩模以暴露焊盘,引线接合焊盘和引线接合焊盘周边上的衬底表面的一部分。 金属凸块设置在凸块焊盘的表面上并延伸到焊接掩模的表面。 金属保护层设置在金属凸块和引线接合焊盘的表面上。 此外,公开了一种用于制造该封装衬底的方法,包括该封装衬底的半导体封装结构及其制造方法。 因此,封装基板的制造工序简单,封装基板变薄。
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公开(公告)号:US20080060838A1
公开(公告)日:2008-03-13
申请号:US11519896
申请日:2006-09-13
申请人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
CPC分类号: H05K3/4682 , H01L21/4857 , H01L21/68 , H01L23/49822 , H01L2924/0002 , H05K3/205 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K2201/0367 , H05K2201/09481 , H05K2201/09563 , H05K2201/096 , H05K2201/099 , H05K2203/0384 , H01L2924/00
摘要: A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.
摘要翻译: 公开了倒装芯片基板结构及其制造方法。 该结构包括建立结构,第一焊接掩模和第二焊接掩模。 分别在堆积结构的第一和第二表面上形成多个第一和第二电接触焊盘。 具有多个开口的第一焊料掩模形成在构建结构的第一表面上,并且开口暴露第一电接触焊盘,其中第一焊接掩模的开口的孔径等于第一电接触焊盘的外径 接触垫 具有多个开口的第二焊料掩模形成在构建结构的第二表面上,并且开口暴露第二电接触焊盘,其中第二焊接掩模的开口的孔径小于第二电接触焊盘的外径 接触垫
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公开(公告)号:US20070249154A1
公开(公告)日:2007-10-25
申请号:US11599983
申请日:2006-11-16
申请人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号: H01L21/4763
CPC分类号: H05K3/4007 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2924/0002 , H05K1/113 , H05K3/0035 , H05K3/108 , H05K3/205 , H05K3/243 , H05K3/28 , H05K3/4682 , H05K2201/09436 , H05K2201/09563 , H05K2201/096 , H05K2203/0152 , H05K2203/0376 , H01L2924/00
摘要: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.
摘要翻译: 公开了一种无芯封装基板的制造方法。 该方法可以制造无芯封装衬底,其包括:至少具有第一焊料掩模和第二焊料掩模的堆积结构,其中在第一和第二焊料掩模中形成多个开口以暴露出 建筑结构; 以及形成在导电焊盘上的多个焊料凸块以及焊料层。 因此,本发明可以生产具有高密度电路布局,较少制造步骤和小尺寸的无芯封装衬底。
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公开(公告)号:US08709940B2
公开(公告)日:2014-04-29
申请号:US13046441
申请日:2011-03-11
申请人: Shing-Ru Wang , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Shing-Ru Wang , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号: H01L21/4763
CPC分类号: H01L23/5389 , H01L24/19 , H01L24/24 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/92244 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517
摘要: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.
摘要翻译: 提出了一种电路板结构及其制造方法。 该结构包括具有多个开口的绝缘保护层,其中形成导电通孔;形成在绝缘保护层的表面上并电连接到绝缘保护层的开口中的导电通孔的图案化电路层,以及 电介质层,其形成在绝缘保护层上和图案化电路层的表面上,其中在电介质层中形成多个开口,从而露出图案化电路层的部分。 因此,本发明可以减小电路板的厚度,减小封装尺寸,提高产品性能,并符合朝向较小型电子器件的发展趋势。
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公开(公告)号:US07820233B2
公开(公告)日:2010-10-26
申请号:US11527632
申请日:2006-09-27
申请人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
发明人: Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号: B05D5/12
CPC分类号: H05K3/4007 , C23C18/1605 , C23C18/165 , C23C18/31 , C25D5/022 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K3/108 , H05K3/205 , H05K3/28 , H05K3/4644 , H05K2201/09472 , H05K2201/09481 , H05K2201/09563 , H05K2201/096 , H05K2203/0384 , H01L2924/00
摘要: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.
摘要翻译: 本发明涉及一种制造倒装芯片基板结构的方法,包括:提供载体; 在载体的表面上形成图案化的抗蚀剂层; 顺序地形成第一金属层,蚀刻停止层和第二金属层; 去除抗蚀剂层,形成图案化的第一焊料掩模,然后在其上形成至少一个第一电路堆积结构; 在电路构建结构上另外形成图案化的第二焊料掩模; 分别去除载体,第一金属层和蚀刻停止层; 以及在电路构建结构的两侧形成焊料凸块。 该方法增加了集成度,达到了小型化的目的。 该方法解决了电路层多重性和工艺复杂度的问题。
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