公开(公告)号：US08830689B2

公开(公告)日：2014-09-09

申请号：US13233851

申请日：2011-09-15

Applicant: Jin Gu Kim ,  Mi Jin Park ,  Young Ho Kim ,  Seung Wook Park ,  Hee Kon Lee ,  Young Do Kweon

Inventor： Jin Gu Kim ,  Mi Jin Park ,  Young Ho Kim ,  Seung Wook Park ,  Hee Kon Lee ,  Young Do Kweon

IPC: H05K7/00 ,  H05K1/11 ,  H05K7/02 ,  H01L23/498 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K3/4694 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/3436 ,  H05K2203/041 ,  H01L2224/0401

Abstract: Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.

Abstract translation: 本发明公开了一种嵌入式嵌入式印刷电路板，包括：基板，其具有在其一面形成并在基板的厚度方向上具有预定高度的空腔; 插入器，其设置在所述空腔中并且包括布线区域和绝缘区域; 以及形成在所述基板中并且包括与所述布线区域的一侧连接的连接图案的电路层。 嵌入式嵌入式印刷电路板的优点在于，嵌入在衬底中，从而可以减小半导体封装的厚度，从而跟上半导体封装变窄的趋势。

公开(公告)号：US08685852B2

公开(公告)日：2014-04-01

申请号：US13222501

申请日：2011-08-31

Applicant: Jin Gu Kim

Inventor： Jin Gu Kim

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.

Abstract translation: 形成半导体器件的金属线的半导体器件和方法包括形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的蚀刻停止层，通过蚀刻蚀刻停止层和第一绝缘层形成的接触孔 绝缘层，形成在接触孔内的接触塞和形成在接触塞和蚀刻停止层之上的第二绝缘层。 蚀刻第二绝缘层以形成沟槽，接触插头通过该沟槽暴露。 金属线形成在沟槽内。 因此，由于金属线之间不会残留具有高介电常数的硬掩模，所以可以减少金属线的电容。

公开(公告)号：US20110207287A1

公开(公告)日：2011-08-25

申请号：US12954321

申请日：2010-11-24

Applicant: Myung Shik LEE ,  Jin Gu KIM

Inventor： Myung Shik LEE ,  Jin Gu KIM

IPC: H01L21/762

CPC classification number: H01L27/11521

Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.

Abstract translation: 一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，在隧道绝缘层上形成包括第一浓度的第一杂质离子的电荷捕获层，形成补偿层，包括第二杂质离子 第二浓度，在电荷陷阱层上方，将补偿层内的第二杂质离子扩散到电荷陷阱层，去除补偿层，在电荷陷阱层的表面上形成电介质层，以及形成用于控制的导电层 电介质层上的栅极。

公开(公告)号：US20110129960A1

公开(公告)日：2011-06-02

申请号：US12929703

申请日：2011-02-09

Applicant: Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

Inventor： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

IPC: H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

Abstract translation: 层叠晶片级封装的制造方法包括：准备基板; 在所述基板上形成导电层; 在导电层上形成芯片连接焊盘和内部连接焊盘; 形成连接到内部连接焊盘的焊球; 将半导体芯片安装在所述导电层上以连接到所述芯片连接焊盘; 形成密封构件以密封焊球和半导体芯片; 将衬底与导电层分离; 通过蚀刻导电层形成重排布线层; 在所述重排布线层上形成外部连接; 在所述密封构件中形成接触孔以暴露所述焊球; 并且堆叠要电连接到通过接触孔暴露的焊料球的电子部件。

公开(公告)号：US20100149770A1

公开(公告)日：2010-06-17

申请号：US12453272

申请日：2009-05-05

Applicant: Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

Inventor： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

IPC: H01L23/538

CPC classification number: H01L25/0652 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips.

Abstract translation: 本发明涉及一种半导体堆叠封装，包括：印刷电路板; 安装在印刷电路板上的第一半导体芯片; 与所述第一半导体芯片并联安装在所述印刷电路板上的第二半导体芯片; 位于第一半导体芯片上的第一重排布线层; 第二重排布线层，与第一重排布线层一起构成一个电路，并且位于第二半导体芯片上; 以及第三半导体芯片，其电连接到第一和第二重排布线层，并且其两端分别位于第一和第二半导体芯片上。

公开(公告)号：US20080217789A1

公开(公告)日：2008-09-11

申请号：US11965827

申请日：2007-12-28

Applicant: Jin Gu KIM

Inventor： Jin Gu KIM

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.

Abstract translation: 形成半导体器件的金属线的半导体器件和方法包括形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的蚀刻停止层，通过蚀刻蚀刻停止层和第一绝缘层形成的接触孔 绝缘层，形成在接触孔内的接触塞和形成在接触塞和蚀刻停止层之上的第二绝缘层。 蚀刻第二绝缘层以形成沟槽，接触插头通过该沟槽暴露。 金属线形成在沟槽内。 因此，由于金属线之间不会残留具有高介电常数的硬掩模，所以可以减少金属线的电容。

公开(公告)号：US06919212B2

公开(公告)日：2005-07-19

申请号：US10741670

申请日：2003-12-18

Applicant: Sang-Hyun Oh ,  Kyu-Hyun Bang ,  In-Woo Jang ,  Jin-Yong Seong ,  Jin-Gu Kim ,  Song-Hee Park ,  Young-Ho Yang ,  Kye-Nam Lee ,  Suk-Kyoung Hong

Inventor： Sang-Hyun Oh ,  Kyu-Hyun Bang ,  In-Woo Jang ,  Jin-Yong Seong ,  Jin-Gu Kim ,  Song-Hee Park ,  Young-Ho Yang ,  Kye-Nam Lee ,  Suk-Kyoung Hong

IPC: H01L27/10 ,  H01L21/00 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.

Abstract translation: 本发明涉及一种制造铁电随机存取存储器（FeRAM）器件的方法。 该方法包括以下步骤：在衬底上形成第一层间绝缘层; 通过穿过所述第一层间绝缘层形成与所述基板的部分部分连接的存储节点接触件; 在所述第一层间绝缘层上形成连接到所述存储节点接点的下电极; 形成具有低于下电极的表面电平的第二层间绝缘层，使得第二层间绝缘层包围下电极的底部; 在所述第二层间绝缘层上形成包围所述下电极的上部的杂质扩散阻挡层; 在下电极和杂质扩散阻挡层上形成铁电层; 以及在所述铁电层上形成顶部电极。

公开(公告)号：US08093124B2

公开(公告)日：2012-01-10

申请号：US12954321

申请日：2010-11-24

Applicant: Myung Shik Lee ,  Jin Gu Kim

Inventor： Myung Shik Lee ,  Jin Gu Kim

IPC: H01L21/225

CPC classification number: H01L27/11521

Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.

Abstract translation: 一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，在隧道绝缘层上形成包括第一浓度的第一杂质离子的电荷捕获层，形成补偿层，包括第二杂质离子 第二浓度，在电荷陷阱层上方，将补偿层内的第二杂质离子扩散到电荷陷阱层，去除补偿层，在电荷陷阱层的表面上形成电介质层，以及形成用于控制的导电层 电介质层上的栅极。

公开(公告)号：US20110309524A1

公开(公告)日：2011-12-22

申请号：US13222501

申请日：2011-08-31

Applicant: Jin Gu KIM

Inventor： Jin Gu KIM

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.

Abstract translation: 形成半导体器件的金属线的半导体器件和方法包括形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的蚀刻停止层，通过蚀刻蚀刻停止层和第一绝缘层形成的接触孔 绝缘层，形成在接触孔内的接触塞和形成在接触塞和蚀刻停止层之上的第二绝缘层。 蚀刻第二绝缘层以形成沟槽，接触插头通过该沟槽暴露。 金属线形成在沟槽内。 因此，由于金属线之间不会残留具有高介电常数的硬掩模，所以可以减少金属线的电容。

公开(公告)号：US08064215B2

公开(公告)日：2011-11-22

申请号：US12230872

申请日：2008-09-05

Applicant: Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

Inventor： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/25 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

Abstract translation: 公开了一种半导体芯片封装和具有嵌入式半导体芯片封装的印刷电路板。 半导体芯片封装可以包括在一侧形成有至少一个芯片焊盘的半导体芯片和形成在半导体芯片的另一侧上的电容器。