公开(公告)号：US08710564B2

公开(公告)日：2014-04-29

申请号：US13418472

申请日：2012-03-13

Applicant: Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

Inventor： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

IPC: H01L27/108

CPC classification number: H01L29/51 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/513

Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

Abstract translation: 本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。 半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及 其电连接到晶体管。 半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括 金属硅酸盐层。 绝缘层可以形成在下电极和上电极之间。

公开(公告)号：US08361551B2

公开(公告)日：2013-01-29

申请号：US12648377

申请日：2009-12-29

Applicant: Jong-Cheol Lee ,  Ki-Yeon Park ,  Jun-Noh Lee

Inventor： Jong-Cheol Lee ,  Ki-Yeon Park ,  Jun-Noh Lee

IPC: C23C16/40

CPC classification number: C23C16/4554 ,  C23C16/45531 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L28/60 ,  H01L29/66575 ,  H01L29/78

Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.

Abstract translation: 在形成具有均匀构成材料组成的目标层的方法中，包括第一中心原子和配体的第一前体在物体的第一反应位置被化学吸附。 然后除去配体或第一中心原子以形成第二反应位点。 包括第二中心原子的第二前体然后在第二反应位点被化学吸附。

公开(公告)号：US20100112777A1

公开(公告)日：2010-05-06

申请号：US12612320

申请日：2009-11-04

Applicant: HanJin LIM ,  Seokwoo Nam ,  Junghee Chung ,  KyoungRyul Yoon ,  Jong-Bom Seo ,  Jun-Noh Lee ,  Sunghoon Bae

Inventor： HanJin LIM ,  Seokwoo Nam ,  Junghee Chung ,  KyoungRyul Yoon ,  Jong-Bom Seo ,  Jun-Noh Lee ,  Sunghoon Bae

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02189 ,  H01L21/02299 ,  H01L21/3141 ,  H01L21/31641 ,  H01L28/91

Abstract: A method of forming a semiconductor device includes forming a bottom electrode having a top surface and a side surface on a semiconductor substrate, performing a tilted ion implantation process to supply ions to the top surface of the bottom electrode and to a portion of the side surface of the bottom electrode, and forming a dielectric layer on the bottom electrode. The formation of the dielectric layer is delayed at the ion-supplied top surface of the bottom electrode and the ion-supplied portion of the side surface of the bottom electrode.

Abstract translation: 一种形成半导体器件的方法包括：在半导体衬底上形成具有顶表面和侧表面的底电极，执行倾斜离子注入工艺以将离子供应到底电极的顶表面和侧表面的一部分 的底部电极，并且在底部电极上形成电介质层。 电介质层的形成在底电极的离子供给顶表面和底电极的侧表面的离子供给部分被延迟。

公开(公告)号：US08698221B2

公开(公告)日：2014-04-15

申请号：US13290397

申请日：2011-11-07

Applicant: Kiyeon Park ,  Insang Jeon ,  Hanjin Lim ,  Yeongcheol Lee ,  Jun-Noh Lee

Inventor： Kiyeon Park ,  Insang Jeon ,  Hanjin Lim ,  Yeongcheol Lee ,  Jun-Noh Lee

IPC: H01L29/92

CPC classification number: H01L28/40 ,  H01G4/20 ,  H01G4/33 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/90

Abstract: A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer.

Abstract translation: 电容器包括第一电极，设置在第一电极上的第一电介质层，第一电介质层具有四方晶体结构并且包括掺杂有第一杂质的第一金属氧化物层，设置在第一金属氧化物层上的第二电介质层 所述第二电介质层具有四方晶系结构并且包括掺杂有第二杂质的第二金属氧化物层，以及设置在所述第二电介质层上的第二电极。 第一电介质层具有比第二电介质层低的结晶温度和更高的介电常数。

公开(公告)号：US20120126300A1

公开(公告)日：2012-05-24

申请号：US13290397

申请日：2011-11-07

Applicant: Kiyeon Park ,  Insang Jeon ,  Hanjin Lim ,  Yeongcheol Lee ,  Jun-Noh Lee

Inventor： Kiyeon Park ,  Insang Jeon ,  Hanjin Lim ,  Yeongcheol Lee ,  Jun-Noh Lee

IPC: H01L27/108 ,  H01G4/20 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01G4/20 ,  H01G4/33 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/90

Abstract: A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer.

Abstract translation: 电容器包括第一电极，设置在第一电极上的第一电介质层，第一电介质层具有四方晶体结构并且包括掺杂有第一杂质的第一金属氧化物层，设置在第一金属氧化物层上的第二电介质层 所述第二电介质层具有四方晶系结构并且包括掺杂有第二杂质的第二金属氧化物层，以及设置在所述第二电介质层上的第二电极。 第一电介质层具有比第二电介质层低的结晶温度和更高的介电常数。

公开(公告)号：US07800162B2

公开(公告)日：2010-09-21

申请号：US12235689

申请日：2008-09-23

Applicant: Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

Inventor： Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

IPC: H01L29/94

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极 绝缘层。 电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。 界面层包括氧氮化硅层。

公开(公告)号：US20100167554A1

公开(公告)日：2010-07-01

申请号：US12648377

申请日：2009-12-29

Applicant: Jong-Cheol LEE ,  Ki-Yeon PARK ,  Jun-Noh LEE

Inventor： Jong-Cheol LEE ,  Ki-Yeon PARK ,  Jun-Noh LEE

IPC: H01L21/469

CPC classification number: C23C16/4554 ,  C23C16/45531 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L28/60 ,  H01L29/66575 ,  H01L29/78

Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.

Abstract translation: 在形成具有均匀构成材料组成的目标层的方法中，包括第一中心原子和配体的第一前体在物体的第一反应位置被化学吸附。 然后除去配体或第一中心原子以形成第二反应位点。 包括第二中心原子的第二前体然后在第二反应位点被化学吸附。

公开(公告)号：US20090127611A1

公开(公告)日：2009-05-21

申请号：US12120443

申请日：2008-05-14

Applicant: Ki-yeon Park ,  Cha-young Yoo ,  Sung-hae Lee ,  Jun-noh Lee ,  Min-kyung Ryu

Inventor： Ki-yeon Park ,  Cha-young Yoo ,  Sung-hae Lee ,  Jun-noh Lee ,  Min-kyung Ryu

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L29/513 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

Abstract: A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer.

Abstract translation: 非易失性存储器件包括包括源区和漏区的半导体层和源区和漏区之间的沟道区; 在半导体层的沟道区上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层，并且包括具有第一厚度的第一氧化物层，高k电介质层和具有不同于第一厚度的第二厚度的第二氧化物层，其顺次层叠在电荷存储层上 ; 和阻挡绝缘层上的控制栅极。

公开(公告)号：US20090159955A1

公开(公告)日：2009-06-25

申请号：US12235689

申请日：2008-09-23

Applicant: Sung-hae LEE ,  Ki-yeon PARK ,  Min-Kyung RYU ,  Myoung-bum LEE ,  Jun-noh LEE

Inventor： Sung-hae LEE ,  Ki-yeon PARK ,  Min-Kyung RYU ,  Myoung-bum LEE ,  Jun-noh LEE

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极 绝缘层。 电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。 界面层包括氧氮化硅层。

公开(公告)号：US20090085160A1

公开(公告)日：2009-04-02

申请号：US12238822

申请日：2008-09-26

Applicant: Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

Inventor： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

IPC: H01L29/92

CPC classification number: H01L29/51 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/513

Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

Abstract translation: 本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。 半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及 其电连接到晶体管。 半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括 金属硅酸盐层。 绝缘层可以形成在下电极和上电极之间。