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    Semiconductor package with chip supporting member
    2.
    发明授权
    Semiconductor package with chip supporting member 失效
    半导体封装带芯片支撑件

    公开(公告)号：US06737737B1

    公开(公告)日：2004-05-18

    申请号：US10355610

    申请日：2003-01-31

    申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

    发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23495

    CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.

    摘要翻译： 提供一种具有芯片支撑构件的半导体封装，包括具有管芯焊盘和多个引线的引线框架，以及安装在管芯焊盘的中心部分的芯片支撑构件。 芯片支撑构件具有附接到管芯焊盘的第一表面和相对的第二表面。 至少芯片安装在芯片支撑部件的第一表面上，以通过芯片支撑部件将芯片与芯片焊盘隔开，以防止芯片被CTE引起的热应力（热膨胀系数 ）芯片和引线框架之间的不匹配，从而消除分层，翘曲和芯片裂纹。 此外，插入在芯片和芯片焊盘之间的芯片支撑构件提供了更大的灵活性，用于在芯片焊盘上安装各种尺寸或形状的芯片，而不必使用对应于芯片焊盘轮廓的芯片。

    MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA
    6.
    发明申请
    MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA 审中-公开
    通过硅的多芯片堆叠结构

    公开(公告)号：US20110227226A1

    公开(公告)日：2011-09-22

    申请号：US13151823

    申请日：2011-06-02

    申请人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    发明人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23/48

    CPC分类号： H01L29/0657 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599

    摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

    摘要翻译： 本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。 该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到 从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。 不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染 的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

    Fabrication method of multi-chip stack structure
    10.
    发明授权
    Fabrication method of multi-chip stack structure 有权
    多芯片堆叠结构的制作方法

    公开(公告)号：US07981729B2

    公开(公告)日：2011-07-19

    申请号：US12818701

    申请日：2010-06-18

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/60

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。