公开(公告)号：US08492808B2

公开(公告)日：2013-07-23

申请号：US13181742

申请日：2011-07-13

申请人： Kazuyuki Omori ,  Kenichi Mori ,  Naohito Suzumura

发明人： Kazuyuki Omori ,  Kenichi Mori ,  Naohito Suzumura

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L27/228 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L43/08 ,  H01L2224/16145 ,  H01L2924/00011 ,  H01L2924/01015 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01004

摘要： In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.

摘要翻译： 在MRAM中，已经使用包裹在铁磁膜中的写入布线来减小写入电流或避免干扰。 此外，通过在Cu布线中添加痕量的Al而获得的CuAl布线被广泛地用于确保高可靠性产品的可靠性。 在高可靠性产品中安装MRAM的可能性很大，因此可靠性很重要。 然而，包层线路增加了原来高的CuAl布线的电阻，因此使用两者可能不能满足布线电阻的规格。 在具有多个铜嵌入布线层的本发明的半导体器件中，构成MRAM的存储单元矩阵区域的多个嵌入铜包布线的铜布线膜由相对纯的铜制成，而CuAl布线膜用作铜布线 在这些布线层下面的铜嵌入的非覆盖布线的膜。

公开(公告)号：US20100044864A1

公开(公告)日：2010-02-25

申请号：US12481234

申请日：2009-06-09

申请人： Kazuyoshi MAEKAWA ,  Kenichi Mori ,  Kazuyuki Omori ,  Yuki Koyama

发明人： Kazuyoshi MAEKAWA ,  Kenichi Mori ,  Kazuyuki Omori ,  Yuki Koyama

IPC分类号： H01L23/48 ,  H01L21/3205

CPC分类号： H01L21/2855 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention aims at providing a method of manufacturing a semiconductor device capable of suppressing metal diffusion from the upper face of wiring.In the present invention, a copper seed film containing copper and a first metal element is formed in a groove formed in a first interlayer film over a semiconductor substrate. After that, a copper plating treatment is performed. After that, a first heat treatment is performed in a first atmosphere in which the copper layer is not oxidized. Then, an excess metal layer of copper alloy is removed and copper alloy wiring is formed in the groove. After that, a second heat treatment is performed in a second atmosphere containing oxygen to form an oxide layer being the oxide of the first metal element over the surface of the copper alloy wiring.

摘要翻译： 本发明的目的在于提供一种能够抑制从布线的上表面的金属扩散的半导体器件的制造方法。 在本发明中，在半导体衬底上形成在第一层间膜中的沟槽中形成含有铜和第一金属元素的铜籽晶膜。 之后，进行镀铜处理。 之后，在铜层未被氧化的第一气氛中进行第一热处理。 然后，除去铜合金的过量金属层，并在槽内形成铜合金布线。 之后，在包含氧的第二气氛中进行第二热处理，以在铜合金布线的表面上形成作为第一金属元件的氧化物的氧化物层。

公开(公告)号：US5739623A

公开(公告)日：1998-04-14

申请号：US494261

申请日：1995-06-23

申请人： Hajime Kanazawa ,  Tetsuya Nishio ,  Kazuki Fujimoto ,  Kazuyuki Omori

发明人： Hajime Kanazawa ,  Tetsuya Nishio ,  Kazuki Fujimoto ,  Kazuyuki Omori

IPC分类号： G02B7/04 ,  G02B7/09 ,  H01L41/09 ,  H02N2/00 ,  H02N2/16 ,  H01L41/08

CPC分类号： H02N2/006 ,  H02N2/106

摘要： A vibration wave driven motor including a stator, a rotor, and an urging member for causing the stator and the rotor to contact each other under pressure. The urging member is supported by a supporting member at a predetermined position. The supporting member is shiftable in the urging direction of the urging member.

摘要翻译： 一种振动波驱动电动机，包括定子，转子和用于使定子和转子在压力下彼此接触的推动构件。 推动构件由预定位置处的支撑构件支撑。 支撑构件能够在施力构件的推动方向上移动。

公开(公告)号：US08227880B2

公开(公告)日：2012-07-24

申请号：US12874894

申请日：2010-09-02

申请人： Mikio Tsujiuchi ,  Yosuke Takeuchi ,  Kazuyuki Omori ,  Kenichi Mori

发明人： Mikio Tsujiuchi ,  Yosuke Takeuchi ,  Kazuyuki Omori ,  Kenichi Mori

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/7833

摘要： To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion. The thickness of the sidewall portion is made greater than that of the bottom wall portion.

摘要翻译： 提供能够对选定的磁阻元件进行写入操作而不引起未选择的磁阻元件的故障的半导体器件和该半导体器件的制造方法。 半导体器件包括具有磁化自由层的磁存储元件，该磁化自由层的磁化方向是可变的，并且形成在引线互连和位于磁存储元件下方的位于第一方向上的数字线，并且能够改变磁化状态 磁化自由层由磁场产生。 数字线包括互连主体部分和覆盖互连体部分的底表面和侧表面并向上敞开的覆层。 包覆层包括覆盖互连主体部分的侧表面的侧壁部分和覆盖互连主体部分的底表面的底壁部分。 侧壁部分的厚度大于底壁部分的厚度。

公开(公告)号：US08125085B2

公开(公告)日：2012-02-28

申请号：US12481234

申请日：2009-06-09

申请人： Kazuyoshi Maekawa ,  Kenichi Mori ,  Kazuyuki Omori ,  Yuki Koyama

发明人： Kazuyoshi Maekawa ,  Kenichi Mori ,  Kazuyuki Omori ,  Yuki Koyama

IPC分类号： H01L23/48 ,  H01L29/80 ,  H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/2855 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

摘要翻译： 半导体器件包括形成在半导体衬底上的层间膜。 在中间膜中形成凹槽。 形成在槽中的布线是包括铜和金属元素的铜合金。 金属元件的氧化物层形成在布线的表面上。 在布线的表面上，沿着铜晶的晶界的第一区域和由晶界包围的第二区域形成氧化物层。 形成在第一区域中的氧化物层的厚度大于在第二区域中形成的氧化物层的厚度。

公开(公告)号：US20120043630A1

公开(公告)日：2012-02-23

申请号：US13181742

申请日：2011-07-13

申请人： Kazuyuki OMORI ,  Kenichi Mori ,  Naohito Suzumura

发明人： Kazuyuki OMORI ,  Kenichi Mori ,  Naohito Suzumura

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L27/228 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L43/08 ,  H01L2224/16145 ,  H01L2924/00011 ,  H01L2924/01015 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01004

摘要： In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.

摘要翻译： 在MRAM中，已经使用包裹在铁磁膜中的写入布线来减小写入电流或避免干扰。 此外，通过在Cu布线中添加痕量的Al而获得的CuAl布线被广泛地用于确保高可靠性产品的可靠性。 在高可靠性产品中安装MRAM的可能性很大，因此可靠性很重要。 然而，包层线路增加了原来高的CuAl布线的电阻，因此使用两者可能不能满足布线电阻的规格。 在具有多个铜嵌入布线层的本发明的半导体器件中，构成MRAM的存储单元矩阵区域的多个嵌入铜包布线的铜布线膜由相对纯的铜制成，而CuAl布线膜用作铜布线 在这些布线层下面的铜嵌入的非覆盖布线的膜。

公开(公告)号：US20110298070A1

公开(公告)日：2011-12-08

申请号：US13150968

申请日：2011-06-01

申请人： Shoichi Fukui ,  Satoshi Iida ,  Shinroku Maejima ,  Kazuyuki Omori

发明人： Shoichi Fukui ,  Satoshi Iida ,  Shinroku Maejima ,  Kazuyuki Omori

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device has a magnetoresistive element, a bit line over the magnetoresistive element, and a yoke cover over the bit line. To form the yoke cover, a laminate film is first formed over the bit line, the laminate film having a first barrier metal layer, a magnetic layer, and a second barrier metal layer which are formed successively over the bit line. Then, the laminate film is subjected to: reactive ion etching with a gas mixture of a carbon tetrafluoride (CF4) gas and an argon (Ar) gas, reactive ion etching with a gas mixture of carbon monoxide (CO), an ammonia (NH3) gas, and an argon (Ar) gas, and reactive ion etching with a gas mixture of a carbon tetrafluoride (CF4) gas and an argon (Ar) gas.

摘要翻译： 半导体器件具有磁阻元件，磁阻元件上的位线和位线上的磁轭盖。 为了形成轭盖，首先在位线上形成层压膜，层压膜具有在位线上连续形成的第一阻挡金属层，磁性层和第二阻挡金属层。 然后，利用四氟化碳（CF 4）气体和氩气（Ar）气体的气体混合物对层压膜进行反应离子蚀刻，用一氧化碳（CO），氨（NH 3）的气体混合物进行反应离子蚀刻 ）气体和氩（Ar）气体，以及用四氟化碳（CF 4）气体和氩气（Ar）气体的气体混合物的反应离子蚀刻。

公开(公告)号：US20110062539A1

公开(公告)日：2011-03-17

申请号：US12885093

申请日：2010-09-17

申请人： Ryoji MATSUDA ,  Motoi Ashida ,  Shuichi Ueno ,  Shoichi Fukui ,  Shinya Hirano ,  Seiji Muranaka ,  Kazuyuki Omori

发明人： Ryoji MATSUDA ,  Motoi Ashida ,  Shuichi Ueno ,  Shoichi Fukui ,  Shinya Hirano ,  Seiji Muranaka ,  Kazuyuki Omori

IPC分类号： H01L29/82 ,  H01L21/04

CPC分类号： H01L27/228 ,  B82Y25/00 ,  H01F10/131 ,  H01F10/14 ,  H01F10/142 ,  H01F10/145 ,  H01F10/20 ,  H01F10/22 ,  H01F10/3254 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76844 ,  H01L27/105 ,  H01L43/08 ,  H01L43/12

摘要： To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.

摘要翻译： 提供抑制重写特性劣化的半导体器件。 在存储单元区域中，半导体磁存储器件中的磁阻元件形成为阵列形状，其方式是将磁阻元件布置在沿一个方向延伸的数字线与沿大致垂直于 数字线。 数字线和位线具有这样一种布线结构，其通过用覆盖层覆盖作为布线主体的铜膜而构成。 磁阻元件的一端侧经由由非磁性材料形成的顶部通孔电耦合到位线。

公开(公告)号：US20110057275A1

公开(公告)日：2011-03-10

申请号：US12874894

申请日：2010-09-02

申请人： Mikio TSUJIUCHI ,  Yosuke Takeuchi ,  Kazuyuki Omori ,  Kenichi Mori

发明人： Mikio TSUJIUCHI ,  Yosuke Takeuchi ,  Kazuyuki Omori ,  Kenichi Mori

IPC分类号： H01L29/66 ,  H01L21/04

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/7833

摘要： To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion. The thickness of the sidewall portion is made greater than that of the bottom wall portion.

摘要翻译： 提供能够对选定的磁阻元件进行写入操作而不引起未选择的磁阻元件的故障的半导体器件和该半导体器件的制造方法。 半导体器件包括具有磁化自由层的磁存储元件，该磁化自由层的磁化方向是可变的，并且形成在引线互连和位于磁存储元件下方的位于第一方向上的数字线，并且能够改变磁化状态 磁化自由层由磁场产生。 数字线包括互连主体部分和覆盖互连体部分的底表面和侧表面并向上敞开的覆层。 包覆层包括覆盖互连主体部分的侧表面的侧壁部分和覆盖互连主体部分的底表面的底壁部分。 侧壁部分的厚度大于底壁部分的厚度。

公开(公告)号：US06658023B1

公开(公告)日：2003-12-02

申请号：US09406029

申请日：1999-09-27

申请人： Kazuyuki Omori ,  Hiroyuki Hatta

发明人： Kazuyuki Omori ,  Hiroyuki Hatta

IPC分类号： H04J316

CPC分类号： H04N21/64307 ,  H04N21/2365 ,  H04N21/4347

摘要： An image transmission system in which when each of a plurality of image signals is transformed into compressed image data compressed at an image compressing portion, the image data are assembled to cells at a cell assembly portion, and the cells from the cell assembly portion are switched at a switching portion, a band controller controls the cell assembly portion so that a band of a transmission line has a value lower than a total band required for a simultaneous transmission of each of the image data. Also, a network controller for controlling band controllers or compression rate controllers at each of communication nodes on a network is provided. Moreover, a sensor which detects a change of an event to control the band controller or the compression rate controller is provided.

摘要翻译： 一种图像传输系统，其中当多个图像信号中的每一个被转换成在图像压缩部分压缩的压缩图像数据时，图像数据被组装到单元组件部分的单元，并且来自单元组合部分的单元被切换 在切换部分，频带控制器控制信元组合部分，使得传输线的频带具有低于同时传输每个图像数据所需的总频带的值。 另外，提供了一种用于在网络上的每个通信节点处控制频带控制器或压缩率控制器的网络控制器。 此外，提供了检测事件变化以控制频带控制器或压缩率控制器的传感器。