公开(公告)号：US20060091560A1

公开(公告)日：2006-05-04

申请号：US11258137

申请日：2005-10-26

Applicant: Jung-Kun Kang ,  Chin-Hsien Lin

Inventor： Jung-Kun Kang ,  Chin-Hsien Lin

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L25/0652 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multi-chip stack package mainly comprises a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate by an active surface facing upwards. The redistribution structure comprises a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.

Abstract translation: 多芯片堆叠封装主要包括基板，第一芯片，再分配结构和至少一个第二芯片。 第一芯片通过面向上的有源表面设置在基板上。 再分布结构包括多个第一中间焊盘，多个第二中间焊盘和多个外部焊盘。 第一中间焊盘，第二中间焊盘和外部焊盘形成在第一芯片的第一有源表面上，其中第一中间焊盘和第二中间焊盘彼此电连接。 第二芯片设置在再分布结构上，并且电连接到第一中间焊盘。 第二中间焊盘通过多个接合线电连接到基板，使得第二芯片和基板被导电，并且键合线的连接长度减小。

公开(公告)号：US20050090043A1

公开(公告)日：2005-04-28

申请号：US10876452

申请日：2004-06-28

Applicant: Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung Tsai

Inventor： Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung Tsai

IPC: H01L21/48 ,  H01L21/68 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/6834 ,  H01L2224/11003 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K3/284 ,  H05K3/3478 ,  H05K2203/0191 ,  H05K2203/041 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A manufacturing method of a ball grid array package mainly comprises providing a carrier unit with an upper surface and a lower surface, mounting a plurality of solder balls on the lower surface of the carrier unit, disposing a protective layer below the lower surface to cover the solder balls, placing a chip on the upper surface of the carrier unit and electrically connecting the carrier and the chip, encapsulating the chip and removing the protective layer so as to form said ball grid array package.

Abstract translation: 球栅阵列封装的制造方法主要包括提供具有上表面和下表面的载体单元，在载体单元的下表面上安装多个焊球，在下表面下方设置保护层以覆盖 焊球，将芯片放置在载体单元的上表面上并电连接载体和芯片，封装芯片并去除保护层，以形成所述球栅阵列封装。

公开(公告)号：US20050023657A1

公开(公告)日：2005-02-03

申请号：US10711575

申请日：2004-09-25

Applicant: Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung-Yueh Tsai

Inventor： Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung-Yueh Tsai

IPC: H01L23/31 ,  H01L23/433 ,  H01L25/10 ,  H01L23/02

CPC classification number: H01L24/73 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/8592 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.

Abstract translation: 提供由多个芯片封装单元组成的堆叠式芯片封装结构。 每个芯片封装单元包括基板，芯片，多根电线，模塑料和多个焊球。 芯片封装单元例如是具有高引脚数的BGA结构，并且一个接一个堆叠并通过焊球电连接。 利用这种结构特征，堆叠的芯片封装结构占据的空间减小，因此整个结构可以小型化。

公开(公告)号：US07218006B2

公开(公告)日：2007-05-15

申请号：US11258137

申请日：2005-10-26

Applicant: Jung-Kun Kang ,  Chin-Hsien Lin

Inventor： Jung-Kun Kang ,  Chin-Hsien Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L25/0652 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multi-chip stack package mainly includes a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate with an active surface facing upwards. The redistribution structure includes a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.

Abstract translation: 多芯片堆叠封装主要包括衬底，第一芯片，再分配结构和至少一个第二芯片。 第一芯片设置在基板上，其表面朝上。 再分配结构包括多个第一中间焊盘，多个第二中间焊盘和多个外部焊盘。 第一中间焊盘，第二中间焊盘和外部焊盘形成在第一芯片的第一有源表面上，其中第一中间焊盘和第二中间焊盘彼此电连接。 第二芯片设置在再分布结构上，并且电连接到第一中间焊盘。 第二中间焊盘通过多个接合线电连接到基板，使得第二芯片和基板被导电，并且键合线的连接长度减小。

公开(公告)号：US07026709B2

公开(公告)日：2006-04-11

申请号：US10711575

申请日：2004-09-25

Applicant: Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung-Yueh Tsai

Inventor： Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung-Yueh Tsai

IPC: H01L23/02 ,  H01L23/34 ,  H01L29/40 ,  H01L23/12 ,  H01L23/29

CPC classification number: H01L24/73 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/8592 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.

Abstract translation: 提供由多个芯片封装单元组成的堆叠式芯片封装结构。 每个芯片封装单元包括基板，芯片，多根电线，模塑料和多个焊球。 芯片封装单元例如是具有高引脚数的BGA结构，并且一个接一个堆叠并通过焊球电连接。 利用这种结构特征，堆叠的芯片封装结构占据的空间减小，因此整个结构可以小型化。

公开(公告)号：USD516192S1

公开(公告)日：2006-02-28

申请号：US29208797

申请日：2004-07-07

Applicant: Sang Kun Kang

Designer： Sang Kun Kang

公开(公告)号：US20050037618A1

公开(公告)日：2005-02-17

申请号：US10878521

申请日：2004-06-29

Applicant: Jun Lee ,  Hyung Park ,  Hyeong Kim ,  Kun Kang

Inventor： Jun Lee ,  Hyung Park ,  Hyeong Kim ,  Kun Kang

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.

Abstract translation: 公开了一种在无引线封装工艺中使用的切割方法。 在切割方法中使用在引线框架的上表面上的成型产品的阵列。 引线框架在模制产品之间具有多个堤坝。 引线框架的下表面附有带子。 每个模制产品包括封装在封装主体中并电耦合到引线框架的上表面的半导体芯片。 通过用封装体作为掩模蚀刻引线框架的上表面，直到每个阻挡层被蚀刻掉为止，完成了分割方法。

公开(公告)号：US20120246371A1

公开(公告)日：2012-09-27

申请号：US13097105

申请日：2011-04-29

Applicant: XIAO-WEI FU ,  ZE-KUN KANG ,  YAN CHEN ,  HUA YUE ,  TAI-CHEN WANG ,  XUE-HONG LIU

Inventor： XIAO-WEI FU ,  ZE-KUN KANG ,  YAN CHEN ,  HUA YUE ,  TAI-CHEN WANG ,  XUE-HONG LIU

IPC: G06F13/00

CPC classification number: G01R31/2808

Abstract: A test apparatus includes a circuit board and a peripheral component interconnect (PCI) expansion slot. A number of golden fingers are arranged at a first side of the circuit board. A second side of the circuit board is connected to a bottom of the PCI expansion slot. The golden fingers are electrically connected to the PCI expansion slot. A number of first test pads and second test pads are arranged on the circuit board between the first and second sides. The first and second test pads have different shapes, sizes, and/or colors. The first and second test pads are electrically connected to the PCI expansion slot correspondingly.

Abstract translation: 测试装置包括电路板和外围组件互连（PCI）扩展槽。 在电路板的第一侧布置有多个金指。 电路板的第二面连接到PCI扩展槽的底部。 金手指电连接到PCI扩展槽。 在第一和第二侧之间的电路板上布置有多个第一测试焊盘和第二测试焊盘。 第一和第二测试垫具有不同的形状，尺寸和/或颜色。 第一和第二测试垫相应地电连接到PCI扩展槽。

公开(公告)号：USD517181S1

公开(公告)日：2006-03-14

申请号：US29208798

申请日：2004-07-07

Applicant: Sang Kun Kang

Designer： Sang Kun Kang

公开(公告)号：US20050230799A1

公开(公告)日：2005-10-20

申请号：US11106554

申请日：2005-04-15

Applicant: Jung-Kun Kang

Inventor： Jung-Kun Kang

IPC: H01L21/50 ,  H01L23/13 ,  H01L23/31 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/141 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18165 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/09072 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multi-chip module comprises a first package and at least a second package. The first package includes a substrate, at least a first chip, an encapsulant, and a plurality of solder balls. The substrate has an upper surface, a lower surface, and at least an opening. The first chip is disposed on the upper surface of the substrate and is electrically connected to the substrate. The encapsulant is formed on the upper surface of the substrate to seal the first chip. In addition, the solder balls are placed on the lower surface of the substrate. The second package is embedded in the opening of the substrate of the first package. The second package includes a plurality of electrical terminals which are exposed out of the first package to be similar to the solder balls for external connection. Accordingly, the solder balls and the electrical terminals can be used as SMT connection terminals of the multi-chip module.

Abstract translation: 多芯片模块包括第一封装和至少第二封装。 第一封装包括衬底，至少第一芯片，密封剂和多个焊球。 基板具有上表面，下表面和至少一个开口。 第一芯片设置在基板的上表面上并与基板电连接。 密封剂形成在基板的上表面上以密封第一芯片。 此外，焊球放置在基板的下表面上。 第二包装被嵌入在第一包装的基板的开口中。 第二封装包括从第一封装暴露出来以类似于用于外部连接的焊球的多个电端子。 因此，焊球和电端子可以用作多芯片模块的SMT连接端子。