公开(公告)号：US07348191B2

公开(公告)日：2008-03-25

申请号：US11473081

申请日：2006-06-23

申请人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

发明人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

摘要翻译： 多个半导体芯片安装在用于制造半导体器件的基板的表面上。 半导体芯片被树脂共同密封，从而形成树脂密封部。 在基板的背面形成有多个焊球，使得相邻的半导体芯片的相应的焊锡球之间的间隔A成为“n”倍（“n”为大于1的整数）焊料间的间隔B 半导体芯片上的球。 在半导体芯片进行电气测试之后，将树脂密封部分和基板切片，从而将半导体芯片分解成块。

公开(公告)号：US20060175715A1

公开(公告)日：2006-08-10

申请号：US11347292

申请日：2006-02-06

申请人： Tetsuya Hirose ,  Naoyuki Shinonaga ,  Shuichi Osaka

发明人： Tetsuya Hirose ,  Naoyuki Shinonaga ,  Shuichi Osaka

IPC分类号： H01L23/28

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes. Then, the capsule type semiconductor package and the logic chip are laminated on the main substrate, and desired connections are provided between the electrodes on the rear surface of the interposer substrate of the capsule type semiconductor package, the electrodes of the logic chip and the electrodes on the front surface of the main substrate. The capsule type semiconductor package and the logic chip are sealed to the front surface of the main substrate by a resin to obtain a system-in-package type semiconductor device.

摘要翻译： 准备分别在其前表面和后表面上具有电极的插入物基板，并且制备具有连接到内部电路的电极的至少一个存储芯片。 然后，将存储芯片的后表面接合到中介基板的前表面，并将存储芯片密封到内插基板的前表面，以构成胶囊型半导体封装。 另一方面，准备了逻辑芯片。 此外，准备分别在前表面和后表面上形成电极的主衬底，并且在这些电极之间设置期望的内部连接。 然后，将胶囊型半导体封装和逻辑芯片层压在主基板上，并且在胶囊型半导体封装的插入器基板的后表面上的电极，逻辑芯片的电极和电极之间设置期望的连接 在主基板的正面上。 胶囊型半导体封装和逻辑芯片通过树脂密封到主基板的前表面，以获得系统级封装型半导体器件。

公开(公告)号：US07642633B2

公开(公告)日：2010-01-05

申请号：US11347292

申请日：2006-02-06

申请人： Tetsuya Hirose ,  Naoyuki Shinonaga ,  Shuichi Osaka

发明人： Tetsuya Hirose ,  Naoyuki Shinonaga ,  Shuichi Osaka

IPC分类号： H01L23/02

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes. Then, the capsule type semiconductor package and the logic chip are laminated on the main substrate, and desired connections are provided between the electrodes on the rear surface of the interposer substrate of the capsule type semiconductor package, the electrodes of the logic chip and the electrodes on the front surface of the main substrate. The capsule type semiconductor package and the logic chip are sealed to the front surface of the main substrate by a resin to obtain a system-in-package type semiconductor device.

摘要翻译： 准备分别在其前表面和后表面上具有电极的插入物基板，并且制备具有连接到内部电路的电极的至少一个存储芯片。 然后，将存储芯片的后表面接合到中介基板的前表面，并将存储芯片密封到内插基板的前表面，以构成封装的胶囊型半导体封装。 另一方面，准备了逻辑芯片。 此外，准备分别在前表面和后表面上形成电极的主衬底，并且在这些电极之间设置期望的内部连接。 然后，将胶囊型半导体封装和逻辑芯片层压在主基板上，并且在胶囊型半导体封装的插入器基板的后表面上的电极，逻辑芯片的电极和电极之间设置期望的连接 在主基板的正面上。 胶囊型半导体封装和逻辑芯片通过树脂密封到主基板的前表面，以获得系统级封装型半导体器件。

公开(公告)号：US06836004B2

公开(公告)日：2004-12-28

申请号：US10342398

申请日：2003-01-15

申请人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

发明人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

IPC分类号： H01L23495

CPC分类号： H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead frame comprises a plurality of frame assemblies. Each framework assembly includes a framework, a suspension lead, a die pad, a plurality of inner leads and outer leads, a first tie bar and a second tie bar, and a lead support. The plurality of framework assemblies are disposed alongside of one another in a direction perpendicular to a direction in which the plurality of outer leads extend. A distance between close-set outer leads in each two neighboring frameworks is substantially n times a pitch of the plurality of outer leads in each framework, wherein n is an integer.

摘要翻译： 引线框架包括多个框架组件。 每个框架组件包括框架，悬挂引线，芯片焊盘，多个内引线和外引线，第一连接杆和第二连接杆以及引线支架。 多个框架组件沿垂直于多个外引线延伸的方向的方向彼此并排设置。 在每个框架中，每个两个相邻框架中紧密集合的外部引线之间的距离基本上是多个外部引线的间距的n倍，其中n是整数。

公开(公告)号：US06724213B2

公开(公告)日：2004-04-20

申请号：US10284284

申请日：2002-10-31

申请人： Daisuke Ito ,  Hiroshi Nakagawa ,  Katsutoshi Ito ,  Naoyuki Shinonaga ,  Shinji Senba

发明人： Daisuke Ito ,  Hiroshi Nakagawa ,  Katsutoshi Ito ,  Naoyuki Shinonaga ,  Shinji Senba

IPC分类号： G01R3126

CPC分类号： G01R1/0416 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a test board for testing semiconductor devices by connecting a plurality of DUTs (semiconductor devices under the test) with a test head, and transmitting test signals from the test head to the plurality of DUTs. The test board comprises a motherboard connected to the test head; a multi-layer wiring board connected to each of the plurality of DUTs; and a scramble board disposed between the motherboard and the multi-layer wiring board. The motherboard and the scramble board, and the multi-layer wiring board and the scramble board are each connected by female connectors and male connectors.

摘要翻译： 提供了一种用于通过将多个DUT（测试中的半导体器件）与测试头连接来测试半导体器件的测试板，以及将测试信号从测试头传输到多个DUT。 测试板包括连接到测试头的主板; 连接到所述多个DUT中的每一个的多层布线基板; 以及设置在母板和多层布线板之间的加扰板。 主板和加扰板，以及多层布线板和加扰板均通过母连接器和公连接器连接。

公开(公告)号：US20090174051A1

公开(公告)日：2009-07-09

申请号：US10585092

申请日：2005-01-12

申请人： Shuichi Osaka ,  Hitoshi Fujimoto ,  Tetsuya Hirose ,  Naoyuki Shinonaga

发明人： Shuichi Osaka ,  Hitoshi Fujimoto ,  Tetsuya Hirose ,  Naoyuki Shinonaga

IPC分类号： H01L25/04 ,  H01L23/48

CPC分类号： H01L25/03 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4917 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure which aims at improvement in function, miniaturization, and systematization of a semiconductor integrated circuit having been made into multichip is offered.A substrate in which a plurality of terminals for a test and a plurality of terminals for external connection are arranged on the front surface, and a plurality of terminals for internal connection are arranged on the back surface, and a semiconductor chip in which a plurality of surface terminals connected to an internal circuit are formed in the front surface are prepared. An encapsulated semiconductor package is formed by joining the back surface of this semiconductor chip to the back surface of the substrate, connecting the surface terminal of the semiconductor chip to the desired terminal for internal connection of the substrate, and sealing the semiconductor chip on the back surface of the substrate with a molded member. A multichip structure is made by joining the encapsulated semiconductor package to another semiconductor chip mounted on the substrate formed external connection terminals and sealing them.

摘要翻译： 提供了一种旨在改进已经制成多芯片的半导体集成电路的功能，小型化和系统化的封装结构。 在前表面上配置有用于测试的多个端子和用于外部连接的多个端子的基板，并且在背面上布置有用于内部连接的多个端子，并且其中多个 在前表面形成连接到内部电路的表面端子。 通过将该半导体芯片的背面接合到基板的背面而形成封装的半导体封装，将半导体芯片的表面端子连接到用于衬底的内部连接的期望端子，并将半导体芯片密封在背面 具有模制构件的基板的表面。 通过将封装的半导体封装连接到安装在形成于基板上的外部连接端子上的另一个半导体芯片并将其密封来制造多芯片结构。

公开(公告)号：US20060240596A1

公开(公告)日：2006-10-26

申请号：US11473081

申请日：2006-06-23

申请人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

发明人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

摘要翻译： 多个半导体芯片安装在用于制造半导体器件的基板的表面上。 半导体芯片被树脂共同密封，从而形成树脂密封部。 在基板的背面形成有多个焊球，使得相邻的半导体芯片的相应的焊锡球之间的间隔A成为“n”倍（“n”为大于1的整数）焊料间的间隔B 半导体芯片上的球。 在半导体芯片进行电气测试之后，将树脂密封部分和基板切片，从而将半导体芯片分解成块。

公开(公告)号：US5537331A

公开(公告)日：1996-07-16

申请号：US269524

申请日：1994-07-01

申请人： Naoyuki Shinonaga

发明人： Naoyuki Shinonaga

IPC分类号： G01R31/26 ,  G01R31/28 ,  G06F11/22 ,  H01L21/66 ,  G01R31/3183

CPC分类号： G06F11/2273

摘要： Disclosed is a method of sequentially conducting a series of tests on devices to be measured starting with a first test up to an Nth test. The method comprises the step of conducting the tests on the plurality of devices to be measured concurrently in sequence starting with the first test. During that time, determination as to whether each of the devices to be measured is defective or non-defective is made each time the test is completed. If it is determined that any of the devices to be measured is defective after any of the series of tests is completed, that defective device alone is replaced with a new device to be measured, and the series of tests are restarted starting with a test subsequent to the test in which the defective device is generated.

摘要翻译： 公开了从第一次测试开始直至第N次测试的顺序对要测量的设备进行一系列测试的方法。 该方法包括从第一次测试开始依次对待测量的多个测试装置进行测试的步骤。 在此期间，每次测试完成时，确定每个要测量的设备是否有缺陷或无缺陷。 如果在完成了一系列测试之后确定要测量的任何设备有缺陷，那么单独的故障设备将被替换为要测量的新设备，并且一系列测试从随后的测试开始重新启动 到生成有缺陷的设备的测试。

公开(公告)号：US07166490B2

公开(公告)日：2007-01-23

申请号：US10336801

申请日：2003-01-06

申请人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

发明人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

IPC分类号： H01L21/44

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the closest solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

摘要翻译： 多个半导体芯片安装在用于制造半导体器件的基板的表面上。 半导体芯片被树脂共同密封，从而形成树脂密封部。 在基板的背面形成多个焊球，使得相邻的半导体芯片的最近的焊球之间的间隔A成为“n”倍（“n”是大于1的整数），焊料间的间隔B 半导体芯片上的球。 在半导体芯片进行电气测试之后，将树脂密封部分和基板切片，从而将半导体芯片分解成块。

公开(公告)号：US06679716B2

公开(公告)日：2004-01-20

申请号：US10324006

申请日：2002-12-20

申请人： Hiroshi Nakagawa ,  Naoyuki Shinonaga ,  Daisuke Ito

发明人： Hiroshi Nakagawa ,  Naoyuki Shinonaga ,  Daisuke Ito

IPC分类号： H01R1122

CPC分类号： H01R31/06 ,  H01R12/721

摘要： A connector enabling wiping operation without changing the distance between a male connector and a female connector and capable of changing connectional association by mechanically operating the connector is obtained. The connector includes a male connector having a male connector terminal, a female connector having a female connector terminal, a relay connector terminal movably mounted on either a male connector body or a female connector body and a drive mechanism part bringing the relay connector terminal into contact with both of the male connector terminal and the female connector terminal and performing rubbing.

摘要翻译： 获得能够进行擦拭操作的连接器，而不改变阳连接器和阴连接器之间的距离并且能够通过机械操作连接器来改变连接关联。 连接器包括具有公连接器端子的公连接器，具有阴连接器端子的阴连接器，可移动地安装在阳连接器主体或阴连接器主体上的中继连接器端子和使中继连接器端子接触的驱动机构部件 与阳连接器端子和母连接器端子两者进行摩擦。