公开(公告)号：US06503840B2

公开(公告)日：2003-01-07

申请号：US09848758

申请日：2001-05-02

申请人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Hong-Qiang Lu ,  Yong-Bae Kim ,  Kiran Kumar ,  Kai Zhang ,  Richard Schinella ,  Philippe Schoenborn

发明人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Hong-Qiang Lu ,  Yong-Bae Kim ,  Kiran Kumar ,  Kai Zhang ,  Richard Schinella ,  Philippe Schoenborn

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843

摘要： A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.

公开(公告)号：US06559048B1

公开(公告)日：2003-05-06

申请号：US09870851

申请日：2001-05-30

申请人： Yong-Bae Kim ,  Philippe Schoenborn ,  Kai Zhang

发明人： Yong-Bae Kim ,  Philippe Schoenborn ,  Kai Zhang

IPC分类号： H01L214763

CPC分类号： H01L21/76804

摘要： Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material. In a preferred embodiment, when the via is cut through several layers of different types of dielectric material, the smoothness of the sloped sidewall of the resulting via is enhanced by adjusting the selectivity of the via etch to uniformly etch each of the layers of dielectric material at approximately the same rate.

摘要翻译： 通过在具有平滑向内倾斜的侧壁的这种介电材料的层中形成通孔来抑制通过在低k含碳氧化硅电介质材料中形成的通孔的中毒。 这样的倾斜的侧壁通孔可以通过首先在这种电介质层的上表面上形成通孔抗蚀剂掩模来在低k电介质层中被蚀刻，然后充分热处理掩模以使抗蚀剂掩模的侧壁几何形状变形以形成倾斜的 侧壁在热处理抗蚀剂掩模的开口或开口上。 在随后的蚀刻步骤中，通过这种倾斜的侧壁抗蚀剂掩模在低k电介质材料中形成通孔，所得到的这种抗蚀剂掩模的侵蚀赋予通孔锥形或倾斜的侧壁几何形状，然后形成在下层 的低k电介质材料。 在优选实施例中，当通孔被切割成若干层不同类型的电介质材料时，通过调节通孔蚀刻的选择性以均匀蚀刻电介质材料的每一层来增强所得通孔的倾斜侧壁的平滑度 大致相同的速度。

公开(公告)号：US06350700B1

公开(公告)日：2002-02-26

申请号：US09607512

申请日：2000-06-28

申请人： Richard D. Schinella ,  Wilbur G. Catabay ,  Philippe Schoenborn

发明人： Richard D. Schinella ,  Wilbur G. Catabay ,  Philippe Schoenborn

IPC分类号： H01L2100

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76813

摘要： A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask. The improved process of the invention comprises: forming a first hard mask layer over an upper layer of low k carbon-doped silicon oxide dielectric material previously formed over an etch stop layer formed over a lower layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first photoresist mask having a pattern of via openings therein over the first hard mask layer; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first hard mask; then removing the first photoresist mask; forming a second hard mask layer over the first hard mask; forming a second photoresist mask having a pattern of trench openings therein over the second hard mask layer; etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first and second hard masks; then removing the second photoresist mask; then using the first and second hard masks to respectively form the via openings in the lower layer of low k carbon-doped silicon oxide dielectric material and trench openings in the upper layer of low k carbon-doped silicon oxide dielectric material; whereby a pattern of via openings and a pattern of trench openings can be formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of the photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings.

公开(公告)号：US07071113B2

公开(公告)日：2006-07-04

申请号：US10619978

申请日：2003-07-14

申请人： Yong-Bae Kim ,  Philippe Schoenborn

发明人： Yong-Bae Kim ,  Philippe Schoenborn

IPC分类号： H01L21/302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  Y10S438/963

摘要： A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.

摘要翻译： 用于去除用于蚀刻集成电路结构的低k碳掺杂氧化硅介电材料中的开口的光致抗蚀剂掩模的工艺，以及用于从抑制开口的蚀刻或去除抗蚀剂掩模中去除残留的蚀刻残留物，同时抑制 对低k电介质材料的损坏包括。 将该结构暴露于还原等离子体以除去光致抗蚀剂掩模的一部分，并除去残留在低k电介质材料层中的开口形成的残余部分。 然后将该结构暴露于氧化等离子体以从低k电介质材料层中的开口或抗蚀剂掩模的去除中除去任何剩余的蚀刻残留物。

公开(公告)号：US06673721B1

公开(公告)日：2004-01-06

申请号：US09898194

申请日：2001-07-02

申请人： Yong-Bae Kim ,  Philippe Schoenborn

发明人： Yong-Bae Kim ,  Philippe Schoenborn

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  Y10S438/963

摘要： A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.

摘要翻译： 用于去除用于蚀刻集成电路结构的低k碳掺杂氧化硅介电材料中的开口的光致抗蚀剂掩模的工艺，以及用于从抑制开口的蚀刻或去除抗蚀剂掩模中去除残留的蚀刻残留物，同时抑制 对低k电介质材料的损坏包括。 将该结构暴露于还原等离子体以除去光致抗蚀剂掩模的一部分，并除去残留在低k电介质材料层中的开口形成的残余部分。 然后将该结构暴露于氧化等离子体以从低k电介质材料层中的开口或抗蚀剂掩模的去除中除去任何剩余的蚀刻残留物。

公开(公告)号：US06969683B2

公开(公告)日：2005-11-29

申请号：US10750348

申请日：2003-12-31

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

摘要翻译： 提供了一种在电介质层中形成双镶嵌互连的方法。 通常，在电介质中蚀刻第一孔。 在电介质的一部分上形成中毒阻挡层，防止抗蚀剂中毒。 在毒物屏障层上形成图案化掩模。 第二孔被蚀刻到电介质层中，其中第一孔的至少一部分具有与第二孔的至少一部分相同的面积。

公开(公告)号：US06713386B1

公开(公告)日：2004-03-30

申请号：US10025304

申请日：2001-12-19

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

公开(公告)号：US5877530A

公开(公告)日：1999-03-02

申请号：US690592

申请日：1996-07-31

申请人： Sheldon Aronowitz ,  Laique Khan ,  Philippe Schoenborn

发明人： Sheldon Aronowitz ,  Laique Khan ,  Philippe Schoenborn

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/7833

摘要： A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation. Since the doped region beneath the oxide spacers includes a gradient doped profile region, with the lightest level of dopant adjacent the channel region (since more of the tapered gate electrode acted as a mask for the initial implantation), the overall dosage level used in the first implantation step to form the gradient doped profile region may be higher than the dosage level conventionally used to form a conventional LDD region. The resistance of the path between the heavily doped drain contact region and the channel region, which includes the gradient doped profile region, is therefore lower than the resistance of a conventional LDD region.

摘要翻译： 公开了一种新颖的集成电路结构及其制造方法，其中在包括MOS器件的衬底中的重掺杂漏极区域和沟道区域之间的半导体衬底中提供锥形或梯度掺杂型态区域。 在本发明的方法中，在第一掺杂步骤期间，以比通常用于形成常规LDD区域的剂量水平，使用类似倒梯形的入口或锥形栅极电极作为掩模。 该掺杂步骤形成具有掺杂剂梯度的掺杂区域，其随着与沟道区域的距离而逐渐增加剂量水平。 然后可以在栅电极的侧壁上形成常规的氧化物间隔物，接着是常规的高电平掺杂，以在氧化物间隔物和场氧化物隔离之间的衬底的未屏蔽部分中形成重掺杂的源极和漏极区。 由于氧化物间隔物下面的掺杂区域包括梯度掺杂的轮廓区域，其中掺杂剂的最弱级别与沟道区域相邻（因为更多的锥形栅极电极用作初始注入的掩模），所以在 形成梯度掺杂轮廓区域的第一注入步骤可以高于常规用于形成常规LDD区域的剂量水平。 因此，重掺杂漏极接触区域和沟道区域（包括梯度掺杂分布区域）之间的路径电阻比常规LDD区域的电阻低。

公开(公告)号：US5413966A

公开(公告)日：1995-05-09

申请号：US179751

申请日：1993-09-09

申请人： Philippe Schoenborn

发明人： Philippe Schoenborn

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/762 ,  H05K1/11 ,  H05K3/46 ,  H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/28026 ,  H01L21/3105 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/7621 ,  H01L21/76227 ,  H01L21/76235 ,  H05K1/115 ,  H05K3/4644 ,  Y10S148/05

摘要： A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The upper layer is deposited to a thickness "t" related to the desired depth "d" of the trenches to be etched. In a second etch step, the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etching of the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity. In either case, trench etch endpoint detection is provided by clearing of the polysilicon and consequent exposure of the lower layer of the trench mask. In both cases, loading effects during the second etch step are alleviated, or completely eliminated, because both the upper layer and the substrate are silicon-based materials.

摘要翻译： 沟槽掩模由沉积在衬底上的两种不同的材料层形成。 两层中较低的一层是绝缘层，如二氧化硅或氮化硅，或两者的组合，两层的上层是掺杂或未掺杂的多晶硅。 一起，在第一蚀刻步骤中图案化两层以形成用于随后蚀刻衬底中的沟槽的沟槽掩模。 上层被沉积成与要蚀刻的沟槽的期望深度“d”相关的厚度“t”。 在第二蚀刻步骤中，在衬底中形成沟槽。 在多晶硅和基板的基本均匀蚀刻的情况下，多晶硅的厚度基本上等于所需的沟槽深度。 在多晶硅和衬底的不均匀蚀刻的情况下，多晶硅的厚度基于蚀刻速率差异。 在任一种情况下，通过清除多晶硅并随后暴露沟槽掩模的下层来提供沟槽蚀刻端点检测。 在这两种情况下，由于上层和衬底都是基于硅的材料，所以在第二蚀刻步骤期间的负载效应被缓解或完全消除。

公开(公告)号：US06579777B1

公开(公告)日：2003-06-17

申请号：US08587417

申请日：1996-01-16

申请人： Ting P. Yen ,  Pamela S. Trammel ,  Philippe Schoenborn ,  Alexander H. Owens

发明人： Ting P. Yen ,  Pamela S. Trammel ,  Philippe Schoenborn ,  Alexander H. Owens

IPC分类号： H01L2176

CPC分类号： H01L21/7621

摘要： A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

摘要翻译： 一种通过在硅衬底中设置开口的方式形成局部氧化的方法，所述局部氧化具有缩小的鸟嘴刺入半导体器件中，所述开口具有从所述凹部开口的垂直轴线测量的具有约10°至约75°之间的锥度的倾斜侧壁， 然后在锥形凹槽开口内生长场氧化物以形成局部氧化。