High impedance electromagnetic surface and method
    1.
    发明申请
    High impedance electromagnetic surface and method 失效
    高阻抗电磁表面和方法

    公开(公告)号:US20070139294A1

    公开(公告)日:2007-06-21

    申请号:US11312286

    申请日:2005-12-20

    IPC分类号: H01Q15/24

    摘要: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates , wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

    摘要翻译: 高阻抗表面(300)具有带有第一表面(314)和第二表面(316)的印刷电路板(302)和设置在印刷的第二表面(316)上的连续导电板(319) 电路板(302)。 多个导电板(318)设置在印刷电路板(302)的第一表面(314)上,同时还提供多个元件。 每个元件包括(1)至少一个电耦合在至少两个导电板(318)之间并嵌入印刷电路板(302)内的多层电感器(330,331)中的至少一个,和(2 )至少一个电耦合在至少两个导电板(318)之间的电容器(320)。 电容器(320)包括设置在相邻导电板之间的(a)介电材料(328)中的至少一个,其中介电材料(328)具有大于6的相对介电常数,以及(b)嵌入的夹层电容器 在印刷电路板(302)内。

    Printed circuit embedded capacitors
    2.
    发明申请
    Printed circuit embedded capacitors 失效
    印刷电路嵌入式电容器

    公开(公告)号:US20050128720A1

    公开(公告)日:2005-06-16

    申请号:US10736327

    申请日:2003-12-15

    摘要: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

    摘要翻译: 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层(505)的第一电极(415),覆盖第一电极的结晶化电介质氧化物芯(405),第二电极 615),以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层(220)。 结晶的电介质氧化物芯的厚度小于1微米,电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

    Integration of monocrystalline oxide devices with fully depleted CMOS on non-silicon substrates
    3.
    发明授权
    Integration of monocrystalline oxide devices with fully depleted CMOS on non-silicon substrates 失效
    在非硅衬底上集成具有完全耗尽CMOS的单晶氧化物器件

    公开(公告)号:US06638872B1

    公开(公告)日:2003-10-28

    申请号:US10255881

    申请日:2002-09-26

    IPC分类号: H01L21311

    摘要: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. Monocrystalline substrates having a hydrogen ion implant are cleaved along the hydrogen ion implant, and an insulating substrate is bonded to the monocrystalline oxide.

    摘要翻译: 通过形成用于生长单晶层的柔性衬底,可以将单晶材料的高质量外延层生长在覆盖单晶衬底(例如大硅晶片)上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外,顺应性衬底的形成可以包括利用表面活性剂增强的单晶硅在单晶氧化物材料上的外延和外延生长。 具有氢离子注入的单晶衬底沿氢离子注入被切割,绝缘衬底与单晶氧化物结合。

    TOUCH SENSORS WITH TACTILE FEEDBACK
    6.
    发明申请
    TOUCH SENSORS WITH TACTILE FEEDBACK 审中-公开
    触摸传感器与触觉反馈

    公开(公告)号:US20100053087A1

    公开(公告)日:2010-03-04

    申请号:US12198199

    申请日:2008-08-26

    IPC分类号: G06F3/02 G06F3/044

    摘要: Touch sensors with one or more piezoelectric elements and devices containing such touch sensors are presented. The touch sensor contains keys that are independently actuated. Contact with a key provides tactile feedback through the piezoelectric element to the user. Each key provides an individual tactile feedback pattern that is dependent on the particular key contacted as well as the function of the key at the time of contact. Actuation of the key provides a different tactile feedback pattern. The piezoelectric element is bonded directly to a printed circuit board, on which electronic components are also mounted.

    摘要翻译: 提供具有一个或多个压电元件和包含这种触摸传感器的装置的触摸传感器。 触摸传感器包含独立启动的按键。 与键的接触通过压电元件向用户提供触觉反馈。 每个键提供一个独立的触觉反馈模式,这取决于所联系的特定键以及键的功能。 钥匙的启动提供了不同的触觉反馈模式。 压电元件直接结合到印刷电路板上,电子元件也安装在印刷电路板上。