公开(公告)号：US09105465B2

公开(公告)日：2015-08-11

申请号：US13053803

申请日：2011-03-22

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L21/02021

摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

摘要翻译： 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

公开(公告)号：US20120241916A1

公开(公告)日：2012-09-27

申请号：US13053803

申请日：2011-03-22

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L29/02 ,  H01L21/302

CPC分类号： H01L21/02021

摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

摘要翻译： 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

公开(公告)号：US08575007B2

公开(公告)日：2013-11-05

申请号：US13073181

申请日：2011-03-28

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC分类号： H01L21/326 ,  H01L21/44

CPC分类号： H01L24/14 ,  G06F17/5068 ,  G06F2217/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/13006 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.

摘要翻译： 本发明包括用于设计倒装芯片的方法及其结果的实施例。 起点是具有半导体衬底的倒装芯片，一个或多个布线层，以及用于接收和发送电流的多个I / O接触焊盘（最后的金属焊盘/接合焊盘）。 还存在用于将I / O接触焊盘连接到另一衬底的多个C4凸块。 然后，确定多个C4凸块中的哪个C4具有达到或超过阈值磁敏度水平的电迁移损伤的敏感性水平，并且作为响应，电镀具有高电流承载能力的导电结构（例如 铜柱，铜基座或部分铜基座）连接到相应的I / O接触焊盘上，并将焊球添加到导电结构的顶部。 所得到的结构是倒装芯片，其中只有少量的C4凸块使用增强的C4（例如铜基座）来减少缺陷的机会。

公开(公告)号：US20120248604A1

公开(公告)日：2012-10-04

申请号：US13073181

申请日：2011-03-28

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC分类号： H01L23/488 ,  G06F17/50

CPC分类号： H01L24/14 ,  G06F17/5068 ,  G06F2217/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/13006 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.

摘要翻译： 本发明包括用于设计倒装芯片的方法及其结果的实施例。 起点是具有用于接收和发送电流的半导体衬底，一个或多个布线层和多​​个I / O接触焊盘（最后的金属焊盘/接合焊盘）的倒装芯片。 还存在用于将I / O接触焊盘连接到另一衬底的多个C4凸块。 然后，确定多个C4凸块中的哪个C4具有达到或超过阈值磁敏度水平的电迁移损伤的敏感性水平，并且作为响应，电镀具有高电流承载能力的导电结构（例如 铜柱，铜基座或部分铜基座）连接到相应的I / O接触焊盘上，并将焊球添加到导电结构的顶部。 所得到的结构是倒装芯片，其中只有少量的C4凸块使用增强的C4（例如铜基座）来减少缺陷的机会。

公开(公告)号：US20130008699A1

公开(公告)日：2013-01-10

申请号：US13615826

申请日：2012-09-14

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H05K1/11 ,  H05K1/09 ,  H05K1/03

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.

摘要翻译： 一个结构。 该结构包括：第一电介质层，其包括顶部电介质表面; 在所述第一电介质层上的导电线; 在所述第一电介质层和所述导电线上的第二电介质层; 所述第二电介质层和所述导电线上的限界冶金（BLM）区域使得所述BLM区电连接到所述导电线; 和BLM区域上的焊球。 BLM区域的特征在于，平行于顶部电介质表面并且完全在BLM区域中的最长直线段的长度不超过预定的最大值，其中预定的最大值最多为 BLM区域的最大水平尺寸的一半在平行于顶部电介质表面的水平方向上测量。

公开(公告)号：US08299611B2

公开(公告)日：2012-10-30

申请号：US12547540

申请日：2009-08-26

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.

摘要翻译： 焊球结构及其形成方法。 该结构包括（i）第一介电层，其包括顶部电介质表面，（ii）导电线，（iii）第二介电层，（iv）球限制冶金（BLM）区域和（v ）焊球。 BLM区域电连接到导电线和焊球。 BLM区域具有与第一介电层的顶部电介质表面平行且完全在BLM区域中的最长直线段的长度不超过预定的最大值的特性。 预定的最大值为平行于第一介电层的顶部电介质表面的水平方向上测量的BLM区域的最大水平尺寸的至多一半。

公开(公告)号：US08592976B2

公开(公告)日：2013-11-26

申请号：US13615826

申请日：2012-09-14

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.

摘要翻译： 一个结构。 该结构包括：第一电介质层，其包括顶部电介质表面; 在所述第一电介质层上的导电线; 在所述第一电介质层和所述导电线上的第二电介质层; 所述第二电介质层和所述导电线上的限界冶金（BLM）区域使得所述BLM区电连接到所述导电线; 和BLM区域上的焊球。 BLM区域的特征在于，平行于顶部电介质表面并且完全在BLM区域中的最长直线段的长度不超过预定的最大值，其中预定的最大值最多为 BLM区域的最大水平尺寸的一半在平行于顶部电介质表面的水平方向上测量。

公开(公告)号：US20100258940A1

公开(公告)日：2010-10-14

申请号：US12547540

申请日：2009-08-26

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.

摘要翻译： 焊球结构及其形成方法。 该结构包括（i）包括顶部电介质表面的第一电介质层，（ii）导电线，（iii）第二电介质层，（iv）球限制冶金（BLM）区域和（v ）焊球。 BLM区域电连接到导电线和焊球。 BLM区域具有与第一介电层的顶部电介质表面平行且完全在BLM区域中的最长直线段的长度不超过预定的最大值的特性。 预定的最大值为平行于第一介电层的顶部电介质表面的水平方向上测量的BLM区域的最大水平尺寸的至多一半。

公开(公告)号：US07547576B2

公开(公告)日：2009-06-16

申请号：US11275867

申请日：2006-02-01

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/00

CPC分类号： H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

摘要： A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.

摘要翻译： 其形成结构及其方法。 半导体结构包括与第一半导体芯片直接物理接触的第一半导体芯片和N个焊料凸块，其中N是正整数。 半导体结构还包括在第一半导体芯片的周边上的第一焊料壁，使得第一焊料壁形成围绕N个焊料凸点的闭环。

公开(公告)号：US07462509B2

公开(公告)日：2008-12-09

申请号：US11383595

申请日：2006-05-16

申请人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

摘要： An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

摘要翻译： 一种封装电子设备的方法。 用于封装器件的方法包括：提供第一衬底，第二衬底和具有第一侧和相对第二侧的集成电路芯片，第一组芯片焊盘和第二组芯片焊盘， 集成电路芯片的第二侧，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的相应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。