Semiconductor eutectic alloy metal (SEAM) technology for fabrication of compliant composite substrates and integration of materials
    4.
    发明授权
    Semiconductor eutectic alloy metal (SEAM) technology for fabrication of compliant composite substrates and integration of materials 失效
    半导体共晶合金金属(SEAM)技术,用于制造柔性复合基板和材料的集成

    公开(公告)号:US06199748B1

    公开(公告)日:2001-03-13

    申请号:US09378769

    申请日:1999-08-20

    IPC分类号: B23K3102

    CPC分类号: B23K20/023

    摘要: A method of semiconductor eutectic alloy metal (SEAM) technology for integration of heterogeneous materials and fabrication of compliant composite substrates takes advantage of eutectic properties of alloys. Sub1 and Sub2 are used to represent the two heterogeneous materials to be bonded or composed into a compliant composite substrate. For the purpose of fabricating compliant composite substrate, the first substrate material (Sub1) combines with the second substrate material (Sub2) to form a composite substrate that controls the stress in the epitaxial layers during cooling. The second substrate material (Sub2) controls the stress in the epitaxial layer grown thereon so that it is compressive during annealing. A joint metal (JM) with a melting point of Tm is chosen to offer variable joint stiffness at different temperatures. JM and Sub1 form a first eutectic alloy at a first eutectic temperature Teu1 while JM and Sub2 form a second eutectic alloy at a second eutectic temperature Teu2. Tm1 and Tm2 are the melting points of Sub1 and Sub2, respectively. The following condition should be met: Tm1, Tm2>Tm>Teu1, Teu2. After cleaning of Sub1 and Sub2, JM is deposited on the bonding sides of Sub1 and Sub2. After preliminary bonding by applying force to press the bonding surfaces together at room temperature, high temperature bonding is subsequently performed, during which the temperature is ramped up to a temperature equal to or higher than Tm. During cooling, JM solidifies first, after which two eutectic alloys solidify.

    摘要翻译: 半导体共晶合金金属(SEAM)技术用于整合异质材料和制造合适的复合材料的方法利用了合金的共晶性能。 Sub1和Sub2用于表示待结合或组成合适的复合衬底的两种异质材料。 为了制造合适的复合衬底,第一衬底材料(Sub1)与第二衬底材料(Sub2)组合以形成控制冷却期间外延层中的应力的复合衬底。 第二衬底材料(Sub2)控制在其上生长的外延层中的应力,使得其在退火期间是压缩的。 选择熔点为Tm的接头金属(JM),以在不同的温度下提供可变接头刚度。 JM和Sub1在第一共晶温度Teu1下形成第一共晶合金,而JM和Sub2在第二共晶温度Teu2下形成第二共晶合金。 Tm1和Tm2分别是Sub1和Sub2的熔点。 应满足以下条件:Tm1,Tm2> Tm> Teu1,Teu2。 在清洗Sub1和Sub2之后,JM沉积在Sub1和Sub2的粘合侧上。 在室温下通过施加力将结合面压合在一起进行初步接合之后,随后进行高温接合,在此期间温度升高至等于或高于Tm的温度。 在冷却过程中,首先固化,然后两个共晶合金固化。

    GROWTH OF III-V LED STACKS USING NANO MASKS
    6.
    发明申请
    GROWTH OF III-V LED STACKS USING NANO MASKS 审中-公开
    使用NANO MASKS的III-V LED堆叠的增长

    公开(公告)号:US20120235115A1

    公开(公告)日:2012-09-20

    申请号:US13355255

    申请日:2012-01-20

    摘要: Methods, semiconductor material stacks and equipment for manufacture of light emitting diodes (LEDs) with improve crystal quality. A growth stopper is deposited between nuclei for a group III-V material, such as GaN, to form a nano mask. The group III-V material is laterally overgrown from a region of the nuclei not covered by the nano mask to form a continuous material layer with reduced dislocation density in preparation for subsequent growth of n-type and p-type layers of the LED. The lateral overgrowth from the nuclei may further recover the surface morphology of the buffer layer despite the presence of the nano mask. Presence of the growth stopper may further result in void formation on a substrate side of an LED stack to improve light extraction efficiency.

    摘要翻译: 方法,用于制造具有改善晶体质量的发光二极管(LED)的半导体材料堆叠和设备。 在诸如GaN的III-V族材料的核之间沉积生长塞,以形成纳米掩模。 III-V族材料从未被纳米掩模覆盖的核的区域横向长满,以形成具有降低的位错密度的连续材料层,以准备LED的n型和p型层的随后生长。 即使存在纳米掩模,来自核的侧向过度生长也可进一步恢复缓冲层的表面形态。 生长停止剂的存在可能进一步导致在LED堆叠的衬底侧上的空隙形成以提高光提取效率。