中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.017 seconds)

    Ultra-low phase noise GaAs MOSFETs
    2.
    发明授权
    Ultra-low phase noise GaAs MOSFETs 失效
    超低相位GaAs MOSFET

    公开(公告)号：US5747838A

    公开(公告)日：1998-05-05

    申请号：US758240

    申请日：1996-11-27

    Applicant: Umesh Kumar Mishra ,  Steven P. DenBaars

    Inventor： Umesh Kumar Mishra ,  Steven P. DenBaars

    IPC: H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/786 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC classification number: H01L29/66477 ,  H01L29/1033 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66742 ,  H01L29/78681

    Abstract: A gallium arsenide-based field effect transistor has a passivation layer of aluminum oxide below a gallium arsenide channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurities, particularly arsenic released in the oxide layer as a result of forming the oxide layer. The low surface state gallium arsenide channel has very low phase noise and is suitable for use as a local oscillator in a heterodyne receiver.

    Abstract translation: 基于砷化镓的场效应晶体管具有在砷化镓沟道下方的氧化铝钝化层和在沟道上形成的氧化铝栅氧化层。 处理氧化铝层以降低表面状态杂质的密度，特别是由于形成氧化物层而在氧化物层中释放的砷的密度。 低表面状态砷化镓通道具有非常低的相位噪声，并且适合用作外差接收器中的本地振荡器。

    High quality, semi-insulating gallium nitride and method and system for forming same
    4.
    发明授权
    High quality, semi-insulating gallium nitride and method and system for forming same 失效
    高品质半绝缘氮化镓及其形成方法及系统

    公开(公告)号：US06261931B1

    公开(公告)日：2001-07-17

    申请号：US09100921

    申请日：1998-06-19

    Applicant: Stacia Keller ,  Bernd Peter Keller ,  Umesh Kumar Mishra ,  Steven P. DenBaars

    Inventor： Stacia Keller ,  Bernd Peter Keller ,  Umesh Kumar Mishra ,  Steven P. DenBaars

    IPC: H01L2120

    CPC classification number: C30B25/02 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262

    Abstract: A method for growing high-quality gallium nitride over a substrate is disclosed. The method comprises growing first layer with a high dislocation density over the substrate, a second layer having a high number of point defects and a reduced dislocation density as compared to the dislocation density of the first layer over the first layer, and a third layer having a reduced number of point defects as compared to the second layer over the second layer. The resulting gallium nitride is semi-insulating, which inhibits parasitic current flow and parasitic capacitive effects, yet it not so insulating that electron flow in adjacent transistor channels is inhibited.

    Abstract translation: 公开了一种在衬底上生长高质量氮化镓的方法。 该方法包括在衬底上生长具有高位错密度的第一层，与第一层上的第一层的位错密度相比，具有大量点缺陷的第二层和减少的位错密度，以及具有 与第二层上的第二层相比减少数量的点缺陷。 所得到的氮化镓是半绝缘的，其抑制寄生电流和寄生电容效应，但是它不会使相邻晶体管沟道中的电子流阻碍而绝缘。

    Enhancement-depletion logic based on gaas mosfets
    5.
    发明授权
    Enhancement-depletion logic based on gaas mosfets 失效
    基于gaas mosfets的增强耗尽逻辑

    公开(公告)号：US5872031A

    公开(公告)日：1999-02-16

    申请号：US757875

    申请日：1996-11-27

    Applicant: Umesh Kumar Mishra ,  Primit A. Parikh

    Inventor： Umesh Kumar Mishra ,  Primit A. Parikh

    IPC: H01L21/28 ,  H01L21/30 ,  H01L21/336 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/51 ,  H01L29/78 ,  H01L29/80 ,  H01L21/8238

    CPC classification number: H01L29/517 ,  H01L21/28264 ,  H01L21/3006 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66522 ,  H01L29/7838 ,  H01L29/802

    Abstract: The present invention discloses a method of forming an oxide layer on a layer of gallium arsenide, including the steps of depositing a layer of aluminum arsenide on the layer of gallium arsenide, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide during the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a GaAs field effect transistor by forming an oxide layer on GaAs and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the gallium arsenide field effect transistor.

    Abstract translation: 本发明公开了一种在砷化镓层上形成氧化物层的方法，包括以下步骤：在砷化镓层上沉积砷化铝层，将砷化铝层暴露于氧化气体混合物，使得 砷化铝被氧化成氧化铝，并且在曝光步骤期间控制在氧化铝中释放的过量的砷，以确保氧化铝中的电性能增强。 该方法用于通过在GaAs上形成氧化物层并且控制多余的砷以在氧化物层中保持高电阻率并避免形成降低晶体管性能的界面表面状态来为GaAs场效应晶体管提供绝缘栅层 。 该方法还用于提供基于砷化镓场效应晶体管的互补金属 - 绝缘体 - 半导体逻辑器件。

    UV assisted gallium nitride growth
    6.
    发明授权
    UV assisted gallium nitride growth 失效
    UV辅助氮化镓生长

    公开(公告)号：US5780355A

    公开(公告)日：1998-07-14

    申请号：US757873

    申请日：1996-11-27

    Applicant: Umesh Kumar Mishra ,  Steven P. DenBaars ,  Stacia Keller

    Inventor： Umesh Kumar Mishra ,  Steven P. DenBaars ,  Stacia Keller

    IPC: H01L21/205 ,  H01L33/00

    CPC classification number: H01L21/0242 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/007

    Abstract: A method for producing Group III nitride films with high indium content and superior optical quality. The Group III nitride film will produce light in the ultraviolet, blue, green, yellow, and red spectral regions. This will enable fabrication of full-color displays and produce a reliable white light source. A metal organic chemical vapor deposition (MOCVD) process in combination with a photochemical process reduces the growth temperature required to produce optical quality Group III nitride films.

    Abstract translation: 一种生产具有高铟含量和优异光学质量的III族氮化物薄膜的方法。 III族氮化物膜将在紫外线，蓝色，绿色，黄色和红色光谱区域产生光。 这将使得能够制造全彩色显示器并产生可靠的白光源。 与光化学工艺结合的金属有机化学气相沉积（MOCVD）工艺降低了生产光学质量III族氮化物膜所需的生长温度。

    GaN/AlGaN/GaN dispersion-free high electron mobility transistors
    7.
    发明授权
    GaN/AlGaN/GaN dispersion-free high electron mobility transistors 失效
    GaN / AlGaN / GaN无分散高电子迁移率晶体管

    公开(公告)号：US07700973B2

    公开(公告)日：2010-04-20

    申请号：US10962911

    申请日：2004-10-12

    Applicant: Likun Shen ,  Sten Johan Heikman ,  Umesh Kumar Mishra

    Inventor： Likun Shen ,  Sten Johan Heikman ,  Umesh Kumar Mishra

    IPC: H01L29/778

    CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7787

    Abstract: A dispersion-free high electron mobility transistor (HEMT), comprised of a substrate; a semi-insulating buffer layer, comprised of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), deposited on the substrate, an AlGaN barrier layer, with an aluminum (Al) mole fraction larger than that of the semi-insulating buffer layer, deposited on the semi-insulating buffer layer, an n-type doped graded AlGaN layer deposited on the AlGaN barrier layer, wherein an Al mole fraction is decreased from a bottom of the n-type doped graded AlGaN layer to a top of the n-type doped graded AlGaN layer, and a cap layer, comprised of GaN or AlGaN with an Al mole fraction smaller than that of the AlGaN barrier layer, deposited on the n-type doped graded AlGaN layer.

    Abstract translation: 一种无分散的高电子迁移率晶体管（HEMT），由衬底组成; 沉积在衬底上的由氮化镓（GaN）或氮化镓铝（AlGaN）组成的半绝缘缓冲层，具有大于半绝缘缓冲层的铝（Al）摩尔分数的AlGaN阻挡层 沉积在半绝缘缓冲层上的沉积在AlGaN阻挡层上的n型掺杂的梯度AlGaN层，其中Al掺杂分数从n型掺杂的梯度AlGaN层的底部减少到n的顶部 型Al掺杂分级AlGaN层，以及由Al或AlGaN构成的覆盖层，其Al分压比AlGaN阻挡层的Al摩尔分数小，形成在n型掺杂的梯度AlGaN层上。

    Gated electrodes for electrolysis and electrosynthesis
    9.
    发明授权
    Gated electrodes for electrolysis and electrosynthesis 有权
    用于电解和电合成的门电极

    公开(公告)号：US08147659B2

    公开(公告)日：2012-04-03

    申请号：US11943363

    申请日：2007-11-20

    Applicant: Rakesh K. Lal ,  Likun Shen ,  Umesh Kumar Mishra

    Inventor： Rakesh K. Lal ,  Likun Shen ,  Umesh Kumar Mishra

    IPC: C25B9/04 ,  C25D17/00

    CPC classification number: C25B1/003 ,  C25B11/0447 ,  Y02P20/135

    Abstract: A gated electrode structure for altering a potential and electric field in an electrolyte near at least one working electrode is disclosed. The gated electrode structure may comprise a gate electrode biased appropriately with respect to a working electrode. Applying an appropriate static or dynamic (time varying) gate potential relative to the working electrode modifies the electric potential and field in an interfacial region between the working electrode and the electrolyte, and increases electron emission to and from states in the electrolyte, thereby facilitating an electrochemical, electrolytic or electrosynthetic reaction and reducing electrode overvoltage/overpotential.

    Abstract translation: 公开了一种用于改变靠近至少一个工作电极的电解质中的电场和电场的选通电极结构。 门电极结构可以包括相对于工作电极适当地偏置的栅电极。 施加相对于工作电极的适当的静态或动态（时变）门电位改变了工作电极和电解质之间的界面区域中的电位和场，并且增加了电解质中的电子发射，从而促进了 电化学，电解或电合成反应和还原电极过电压/超电势。

Patent Agency Ranking