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    ENHANCED DISPLAY FOR PRESENTING TACHOMETER INFORMATION
    1.
    发明申请
    ENHANCED DISPLAY FOR PRESENTING TACHOMETER INFORMATION 审中-公开
    用于提供测速仪信息的增强显示

    公开(公告)号：US20080306636A1

    公开(公告)日：2008-12-11

    申请号：US11758880

    申请日：2007-06-06

    Applicant: Martin Jay Caspe-Detzer ,  Andrew Joseph Ressa ,  Phu Vi Tran ,  Ian David O'Connor ,  John William Espinosa ,  Paul Stephen Crowe

    Inventor： Martin Jay Caspe-Detzer ,  Andrew Joseph Ressa ,  Phu Vi Tran ,  Ian David O'Connor ,  John William Espinosa ,  Paul Stephen Crowe

    IPC: B60Q1/54 ,  G01P3/42

    CPC classification number: G01P1/08 ,  F02B77/084

    Abstract: Aspects of the present invention are directed at an enhanced display for presenting tachometer information. In accordance with one embodiment, a method is provided that causes an electronic control unit associated with a dashboard display to present the current engine speed (e.g. RPM) relative to an optimal range in which fuel efficiency is maximized. More specifically, the method includes obtaining a set of tachometer data at the electronic control unit that defines the lower and upper limits of the optimal range in which fuel efficiency is maximized. Periodically, the current engine speed may be obtained by the electronic control unit associated with the dashboard display. Then, the method causes the current engine speed to be presented on the graphical display relative to the lower and upper limits of the optimal range.

    Abstract translation: 本发明的方面涉及用于呈现转速计信息的增强显示。 根据一个实施例，提供一种方法，其使得与仪表板显示相关联的电子控制单元相对于燃料效率最大化的最佳范围呈现当前发动机转速（例如RPM）。 更具体地，该方法包括在电子控制单元处获得一组限定了燃料效率最大化的最佳范围的下限和上限的转速计数据。 周期性地，可以通过与仪表板显示相关联的电子控制单元来获得当前的发动机转速。 然后，该方法使得当前发动机转速相对于最佳范围的下限和上限呈现在图形显示器上。

    Delay locked loop circuitry for clock delay adjustment
    3.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    Applicant: Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    Inventor： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC: H04L700

    CPC classification number: H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    Abstract translation: 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay-locked loop circuitry for clock delay adjustment
    4.
    发明授权
    Delay-locked loop circuitry for clock delay adjustment 失效
    用于时钟延迟调整的延迟锁定环路

    公开(公告)号：US6125157A

    公开(公告)日：2000-09-26

    申请号：US795657

    申请日：1997-02-06

    Applicant: Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    Inventor： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    IPC: G06F1/10 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/24 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

    CPC classification number: H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H04L7/0008 ,  H04L7/0025

    Abstract: Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.

    Abstract translation: 延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    FUEL GELLING PREVENTION USING ENGINE AUTO START FUNCTIONALITY
    7.
    发明申请
    FUEL GELLING PREVENTION USING ENGINE AUTO START FUNCTIONALITY 审中-公开

    公开(公告)号：US20200072123A1

    公开(公告)日：2020-03-05

    申请号：US16119310

    申请日：2018-08-31

    Applicant: David Bruce ,  Phu Vi Tran ,  Brendan A. Smith

    Inventor： David Bruce ,  Phu Vi Tran ,  Brendan A. Smith

    IPC: F02B77/08 ,  F02M37/00 ,  F02M31/125 ,  F02M31/16 ,  F02N11/08

    Abstract: In some embodiments, a fuel temperature sensor is located proximate to a vehicle component that is expected to experience fuel gelling, such as near or within a fuel filter, in order to obtain temperature information that accurately reflects the likelihood of fuel gelling occurring within the component. The proximate fuel temperature sensor can provide more accurate temperature information for components such as fuel filters that are installed at the periphery of the vehicle, compared to other temperature sensors that measure oil temperatures or other temperatures of centrally located vehicle components. In some embodiments, the vehicle is automatically started when the temperature indicated by the fuel temperature sensor falls below a startup temperature threshold value, and is automatically stopped after a predetermined time period or after the temperature reaches a shutdown temperature threshold value.

    Vehicle countdown timer and user interface
    8.
    发明授权
    Vehicle countdown timer and user interface 有权
    车辆倒计时器和用户界面

    公开(公告)号：US08049605B2

    公开(公告)日：2011-11-01

    申请号：US13011685

    申请日：2011-01-21

    Applicant: Martin Jay Caspe-Detzer ,  Andrew Joseph Ressa ,  Phu Vi Tran ,  Ian David O'Connor ,  John William Espinosa ,  Paul Stephen Crowe

    Inventor： Martin Jay Caspe-Detzer ,  Andrew Joseph Ressa ,  Phu Vi Tran ,  Ian David O'Connor ,  John William Espinosa ,  Paul Stephen Crowe

    IPC: G08B21/00

    CPC classification number: F02D41/042 ,  F02D2200/604

    Abstract: Aspects of the present invention are directed at allowing a vehicle to idle for a predetermined amount of time before shutdown. In accordance with one embodiment, a method is provided that accepts input from the vehicle operator to initiate a countdown to vehicle shutdown. When the input is received, a countdown is initiated that is regularly updated to reflect the passage of time. During the countdown, a vehicle ignition bus is maintained in an active state and a countdown value that reflects the time remaining before shutdown is presented on a graphical display. Then, in response to expiration of the countdown, the method allows the vehicle ignition bus to transition into an inactive state.

    Abstract translation: 本发明的方面涉及允许车辆在停机之前怠速预定的时间量。 根据一个实施例，提供了一种接受来自车辆操作者的输入以启动对车辆关闭的倒计时的方法。 当收到输入时，启动定期更新的倒计时反映时间的流逝。 在倒计时期间，车辆点火总线保持在活动状态，并且在图形显示器上呈现反映停机之前剩余时间的倒计时值。 然后，响应于倒数计时结束，该方法允许车辆点火总线转换到非活动状态。

    PROCESS FOR PREPARING ALKANE LIQUIDS FOR USE IN IMMERSION LITHOGRAPHY
    9.
    发明申请
    PROCESS FOR PREPARING ALKANE LIQUIDS FOR USE IN IMMERSION LITHOGRAPHY 审中-公开
    用于制备浸出液中使用的碱性液体的方法

    公开(公告)号：US20090299113A1

    公开(公告)日：2009-12-03

    申请号：US12128020

    申请日：2008-05-28

    Applicant: Douglas J. Adelman ,  Hoang Vi Tran

    Inventor： Douglas J. Adelman ,  Hoang Vi Tran

    IPC: C07C5/02

    CPC classification number: C07C7/163 ,  C07C9/00

    Abstract: A method for purifying liquid alkanes, especially dicyclic alkanes, for use in immersion lithography is provided. The method produces alkanes having absorbance at 193 nm of ≦0.1/cm, and residue of ≦100 ppm. The liquid alkane compositions are useful as immersion liquids in photomicrolithography employed for production of electronic circuits.

    Abstract translation: 提供了用于浸没式光刻中使用的用于净化液态烷烃，特别是二环烷烃的方法。 该方法产生在193nm处具有<= 0.1 / cm的吸光度和<= 100ppm的残留物的烷烃。 液体烷烃组合物可用作用于生产电子电路的微光刻中的浸液。

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