公开(公告)号：US12249599B2

公开(公告)日：2025-03-11

申请号：US18194236

申请日：2023-03-31

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US12068324B2

公开(公告)日：2024-08-20

申请号：US17358790

申请日：2021-06-25

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01G4/228 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L49/02 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

公开(公告)号：US11728266B2

公开(公告)日：2023-08-15

申请号：US17133096

申请日：2020-12-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/585 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32145

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US20230062454A1

公开(公告)日：2023-03-02

申请号：US17461207

申请日：2021-08-30

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai

IPC: H01L23/053 ,  H01L23/10

Abstract: Modules and methods of assembly are described. A module includes a lid mounted on a module substrate and covering a component. A stiffener structure may optionally be mounted between the lid and module substrate. A recess can be formed in any of an outer wall bottom surface of the lid, and top or bottom surface of the stiffener structure such that an adhesive layer at least partially fills the recess.

公开(公告)号：US11587909B2

公开(公告)日：2023-02-21

申请号：US16991908

申请日：2020-08-12

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/24 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：US11545455B2

公开(公告)日：2023-01-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US11515261B2

公开(公告)日：2022-11-29

申请号：US17027097

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai

IPC: H01L23/538 ,  H01L25/16 ,  H05K1/18 ,  H01L21/56 ,  H01L23/485

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

公开(公告)号：US20220320048A1

公开(公告)日：2022-10-06

申请号：US17848219

申请日：2022-06-23

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065 ,  H01L25/00 ,  H01L49/02 ,  H01L23/528 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L25/16

Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.

公开(公告)号：US20220013504A1

公开(公告)日：2022-01-13

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20210398980A1

公开(公告)日：2021-12-23

申请号：US17358790

申请日：2021-06-25

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01L23/13 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L23/498 ,  H01G4/228 ,  H01L49/02 ,  H01L23/48

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.