公开(公告)号：US07422664B2

公开(公告)日：2008-09-09

申请号：US11346785

申请日：2006-02-03

Applicant: Alan Alexander Ritchie ,  Adolph Miller Allen

Inventor： Alan Alexander Ritchie ,  Adolph Miller Allen

IPC: C23C14/34

CPC classification number: H01J37/32009

Abstract: A method for igniting a plasma in a semiconductor process chamber is provided herein. In one embodiment, a method for igniting a plasma in a semiconductor substrate process chamber having an electrically isolated anode, wherein the plasma has failed to ignite upon applying a plasma ignition voltage to a cathode of the process chamber, includes the steps of reducing the magnitude of the voltage applied to the cathode; reapplying the plasma ignition voltage to the cathode; and monitoring the process chamber to determine if the plasma has ignited. The step of monitoring the process chamber may have a duration of a first period of time. The step of reducing the magnitude of the voltage applied to the cathode may have a duration of a second period of time. The steps of reducing the cathode voltage magnitude and reapplying the plasma ignition voltage may be repeated until a plasma ignites.

Abstract translation: 本文提供了一种用于点燃半导体处理室中的等离子体的方法。 在一个实施例中，一种用于点燃具有电隔离阳极的半导体衬底处理室中的等离子体的方法，其中等离子体在将等离子体点火电压施加到处理室的阴极时不能点燃，包括降低幅度的步骤 施加到阴极的电压; 将等离子体点火电压重新施加到阴极; 并监测处理室以确定等离子体是否已点燃。 监测处理室的步骤可以具有第一时间段的持续时间。 降低施加到阴极的电压的大小的步骤可以具有第二时间段的持续时间。 可以重复降低阴极电压幅度并重新施加等离子体点火电压的步骤，直到等离子体点燃。

公开(公告)号：US09127362B2

公开(公告)日：2015-09-08

申请号：US11553982

申请日：2006-10-27

Applicant: Kathleen Scheible ,  Michael Allen Flanigan ,  Goichi Yoshidome ,  Adolph Miller Allen ,  Cristopher M. Pavloff

Inventor： Kathleen Scheible ,  Michael Allen Flanigan ,  Goichi Yoshidome ,  Adolph Miller Allen ,  Cristopher M. Pavloff

IPC: C23C14/00 ,  C23C14/50 ,  H01L21/687 ,  C23C14/34 ,  H01J37/34

CPC classification number: H01J37/3488 ,  C23C14/3407 ,  C23C14/50 ,  H01J37/34 ,  H01J37/3441 ,  H01J37/3447 ,  H01L21/68735

Abstract: A process kit comprises a ring assembly that is placed about a substrate support in a substrate processing chamber to reduce deposition of process deposits on the chamber components and on an overhang edge of the substrate. The process kit includes a deposition ring, cover ring, and anti-lift bracket, and can also include a unitary shield. A target is also described.

Abstract translation: 处理套件包括环组件，该环组件围绕衬底处理室中的衬底支撑件放置，以减少工艺沉积物沉积在腔室部件上以及衬底的突出边缘上的沉积。 处理套件包括沉积环，盖环和防起重托架，并且还可以包括整体式护罩。 还描述了一个目标。

公开(公告)号：US20130087452A1

公开(公告)日：2013-04-11

申请号：US13662391

申请日：2012-10-26

Applicant: Lara Hawrylchak ,  Kirankumar Savandaiah ,  Muhammed M. Rasheed ,  Rongjun Wang ,  Adolph Miller Allen ,  Zhigang Xie

Inventor： Lara Hawrylchak ,  Kirankumar Savandaiah ,  Muhammed M. Rasheed ,  Rongjun Wang ,  Adolph Miller Allen ,  Zhigang Xie

IPC: H01L21/67

CPC classification number: H01L21/67017 ,  C23C14/34 ,  C23C14/564 ,  H01J37/3408 ,  H01J37/3447

Abstract: Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a cover ring, a shield, and an isolator for use in a physical deposition chamber. The components of the process kit work alone and in combination to significantly reduce particle generation and stray plasmas. In comparison with existing multiple part shields, which provide an extended RF return path contributing to RF harmonics causing stray plasma outside the process cavity, the components of the process kit reduce the RF return path thus providing improved plasma containment in the interior processing region.

公开(公告)号：US20130075246A1

公开(公告)日：2013-03-28

申请号：US13622769

申请日：2012-09-19

Applicant: Zhenbin Ge ,  Alan Ritchie ,  Adolph Miller Allen

Inventor： Zhenbin Ge ,  Alan Ritchie ,  Adolph Miller Allen

IPC: H01L21/02

CPC classification number: H01L21/02521 ,  C23C14/14 ,  C23C14/34 ,  C23C14/3492 ,  C23C14/54 ,  C23C14/5826 ,  C23C14/5833 ,  C23C14/584 ,  C23C14/5873 ,  H01L21/2855 ,  H01L21/76838

Abstract: Methods for forming a metal containing layer onto a substrate with good deposition profile control and film uniformity across the substrate are provided. In one embodiment, a method of sputter depositing a metal containing layer on the substrate includes transferring a substrate in a processing chamber, supplying a gas mixture including at least Ne gas into the processing chamber, applying a RF power to form a plasma from the gas mixture, and depositing a metal containing layer onto the substrate in the presence of the plasma.

Abstract translation: 提供了在衬底上形成含金属层的方法，其具有良好的沉积轮廓控制和跨衬底的膜均匀性。 在一个实施例中，在衬底上溅射沉积含金属层的方法包括在处理室中转移衬底，将至少包含Ne气体的气体混合物供应到处理室中，施加RF功率以从气体形成等离子体 混合物，并在存在等离子体的情况下将含金属的层沉积到衬底上。

公开(公告)号：US07829456B2

公开(公告)日：2010-11-09

申请号：US12257279

申请日：2008-10-23

Applicant: Winsor Lam ,  Tza-Jing Gung ,  Hong S. Yang ,  Adolph Miller Allen

Inventor： Winsor Lam ,  Tza-Jing Gung ,  Hong S. Yang ,  Adolph Miller Allen

IPC: H01L21/4763

CPC classification number: H01L21/76841 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing substrates includes providing to a process chamber a substrate comprising an exposed dielectric layer having a feature formed therein. A mask layer comprising titanium nitride may be selectively deposited atop corners of the feature. A barrier layer may be selectively deposited atop the mask layer and into a bottom portion of the feature. The barrier layer deposited on the bottom portion of the feature may be etched to redistribute at least a portion of the barrier layer onto sidewalls of the feature.

Abstract translation: 本文提供了处理基板的方法。 在一些实施例中，用于处理衬底的方法包括向处理室提供包括其中形成有特征的暴露介电层的衬底。 包括氮化钛的掩模层可以选择性地沉积在特征的角落的顶部。 阻挡层可以选择性地沉积在掩模层的顶部并进入特征的底部。 可以蚀刻沉积在特征的底部上的阻挡层，以将阻挡层的至少一部分重新分布到特征的侧壁上。

公开(公告)号：US20100252417A1

公开(公告)日：2010-10-07

申请号：US12754473

申请日：2010-04-05

Applicant: Adolph Miller Allen ,  Lara Hawrylchak ,  Zhigang Xie ,  Muhammad M. Rasheed ,  Rongjun Wang ,  Xianmin Tang ,  Zhendong Liu ,  Tza-Jing Gung ,  Srinivas Gandikota ,  Mei Chang ,  Michael S. Cox ,  Donny Young ,  Kirankumar Savandaiah ,  Zhenbin Ge

Inventor： Adolph Miller Allen ,  Lara Hawrylchak ,  Zhigang Xie ,  Muhammad M. Rasheed ,  Rongjun Wang ,  Xianmin Tang ,  Zhendong Liu ,  Tza-Jing Gung ,  Srinivas Gandikota ,  Mei Chang ,  Michael S. Cox ,  Donny Young ,  Kirankumar Savandaiah ,  Zhenbin Ge

IPC: C23C14/34

CPC classification number: C23C14/564 ,  C23C14/345 ,  C23C14/3492 ,  C23C14/35 ,  C23C14/548 ,  H01J37/32642 ,  H01J37/3405 ,  H01J37/3408 ,  H01J37/3441 ,  H01J37/3455

Abstract: Embodiments of the invention generally provide a processing chamber used to perform a physical vapor deposition (PVD) process and methods of depositing multi-compositional films. The processing chamber may include: an improved RF feed configuration to reduce any standing wave effects; an improved magnetron design to enhance RF plasma uniformity, deposited film composition and thickness uniformity; an improved substrate biasing configuration to improve process control; and an improved process kit design to improve RF field uniformity near the critical surfaces of the substrate. The method includes forming a plasma in a processing region of a chamber using an RF supply coupled to a multi-compositional target, translating a magnetron relative to the multi-compositional target, wherein the magnetron is positioned in a first position relative to a center point of the multi-compositional target while the magnetron is translating and the plasma is formed, and depositing a multi-compositional film on a substrate in the chamber.

Abstract translation: 本发明的实施例通常提供用于执行物理气相沉积（PVD）工艺的处理室和沉积多组分膜的方法。 处理室可以包括：改进的RF馈送配置以减少任何驻波效应; 改进的磁控管设计，以增强RF等离子体均匀性，沉积膜组成和厚度均匀性; 改进的衬底偏置结构以改善工艺控制; 以及改进的工艺组件设计，以改善衬底临界表面附近的RF场均匀性。 该方法包括使用耦合到多组分靶的RF电源在室的处理区域中形成等离子体，相对于多组分靶物平移磁控管，其中磁控管相对于中心点位于第一位置 的多组分靶，同时磁控管正在平移并且形成等离子体，并且在腔室中的基底上沉积多组分膜。

公开(公告)号：US20080308416A1

公开(公告)日：2008-12-18

申请号：US11764772

申请日：2007-06-18

Applicant: Adolph Miller Allen ,  Ki Hwan Yoon ,  Ted Guo ,  Hong S. Yang ,  Sang-Ho Yu

Inventor： Adolph Miller Allen ,  Ki Hwan Yoon ,  Ted Guo ,  Hong S. Yang ,  Sang-Ho Yu

IPC: C23C14/34

CPC classification number: C23C14/3407 ,  H01J37/3423 ,  H01J37/3435

Abstract: A sputtering target for a sputtering chamber comprises a backing plate with a sputtering plate mounted thereon. In one version, the backing plate comprises a circular plate having a front surface comprising an annular groove. The sputtering plate comprises a disk comprising a sputtering surface and a backside surface having a circular ridge that is shaped and sized to fit into the annular groove of the backing plate.

Abstract translation: 用于溅射室的溅射靶包括安装有溅射板的背板。 在一个版本中，背板包括具有包括环形凹槽的前表面的圆形板。 溅射板包括包括溅射表面的圆盘和具有圆形脊的后侧表面，该圆形脊的形状和尺寸适于装配到背板的环形槽中。

公开(公告)号：US08968536B2

公开(公告)日：2015-03-03

申请号：US11764772

申请日：2007-06-18

Applicant: Adolph Miller Allen ,  Ki Hwan Yoon ,  Ted Guo ,  Hong S. Yang ,  Sang-Ho Yu

Inventor： Adolph Miller Allen ,  Ki Hwan Yoon ,  Ted Guo ,  Hong S. Yang ,  Sang-Ho Yu

IPC: C23C14/35 ,  C23C14/34 ,  H01J37/34

CPC classification number: C23C14/3407 ,  H01J37/3423 ,  H01J37/3435

Abstract: A sputtering target for a sputtering chamber comprises a backing plate with a sputtering plate mounted thereon. In one version, the backing plate comprises a circular plate having a front surface comprising an annular groove. The sputtering plate comprises a disk comprising a sputtering surface and a backside surface having a circular ridge that is shaped and sized to fit into the annular groove of the backing plate.

Abstract translation: 用于溅射室的溅射靶包括安装有溅射板的背板。 在一个版本中，背板包括具有包括环形凹槽的前表面的圆形板。 溅射板包括包括溅射表面的圆盘和具有圆形脊的后侧表面，该圆形脊的形状和尺寸适于装配到背板的环形槽中。

公开(公告)号：US09218961B2

公开(公告)日：2015-12-22

申请号：US13622769

申请日：2012-09-19

Applicant: Zhenbin Ge ,  Alan Ritchie ,  Adolph Miller Allen

Inventor： Zhenbin Ge ,  Alan Ritchie ,  Adolph Miller Allen

IPC: C23C14/24 ,  H01L21/02 ,  C23C14/58 ,  C23C14/54 ,  H01L21/285 ,  H01L21/768 ,  C23C14/14 ,  C23C14/34

CPC classification number: H01L21/02521 ,  C23C14/14 ,  C23C14/34 ,  C23C14/3492 ,  C23C14/54 ,  C23C14/5826 ,  C23C14/5833 ,  C23C14/584 ,  C23C14/5873 ,  H01L21/2855 ,  H01L21/76838

Abstract: Methods for forming a metal containing layer onto a substrate with good deposition profile control and film uniformity across the substrate are provided. In one embodiment, a method of sputter depositing a metal containing layer on the substrate includes transferring a substrate in a processing chamber, supplying a gas mixture including at least Ne gas into the processing chamber, applying a RF power to form a plasma from the gas mixture, and depositing a metal containing layer onto the substrate in the presence of the plasma.

Abstract translation: 提供了在衬底上形成含金属层的方法，其具有良好的沉积轮廓控制和跨衬底的膜均匀性。 在一个实施例中，在衬底上溅射沉积含金属层的方法包括在处理室中转移衬底，将至少包含Ne气体的气体混合物供应到处理室中，施加RF功率以从气体形成等离子体 混合物，并在存在等离子体的情况下将含金属的层沉积到衬底上。

公开(公告)号：US20110036709A1

公开(公告)日：2011-02-17

申请号：US12850312

申请日：2010-08-04

Applicant: Lara Hawrylchak ,  Kirankumar Savandaiah ,  Muhammad M. Rasheed ,  Rongjun Wang ,  Adolph Miller Allen ,  Zhigang Xie

Inventor： Lara Hawrylchak ,  Kirankumar Savandaiah ,  Muhammad M. Rasheed ,  Rongjun Wang ,  Adolph Miller Allen ,  Zhigang Xie

IPC: C23C14/34

CPC classification number: H01L21/67017 ,  C23C14/34 ,  C23C14/564 ,  H01J37/3408 ,  H01J37/3447

Abstract: Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a cover ring, a shield, and an isolator for use in a physical deposition chamber. The components of the process kit work alone and in combination to significantly reduce particle generation and stray plasmas. In comparison with existing multiple part shields, which provide an extended RF return path contributing to RF harmonics causing stray plasma outside the process cavity, the components of the process kit reduce the RF return path thus providing improved plasma containment in the interior processing region.

Abstract translation: 本发明的实施例一般涉及用于半导体处理室的处理套件和具有套件的半导体处理室。 更具体地，本文所述的实施例涉及包括用于物理沉积室中的盖环，屏蔽和隔离器的处理套件。 过程组件的组件单独工作并组合起来，以显着减少颗粒产生和杂散等离子体。 与现有的多部分屏蔽相比，其提供了有助于RF谐波的扩展的RF返回路径，从而在处理空腔之外引起杂散等离子体，处理套件的部件降低了RF返回路径，从而在内部处理区域中提供了改进的等离子体容纳物。