公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09502363B2

公开(公告)日：2016-11-22

申请号：US14223805

申请日：2014-03-24

申请人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US09281293B2

公开(公告)日：2016-03-08

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09997492B2

公开(公告)日：2018-06-12

申请号：US14086745

申请日：2013-11-21

申请人： Weng F. Yap ,  Scott M. Hayes ,  Alan J. Magnus

发明人： Weng F. Yap ,  Scott M. Hayes ,  Alan J. Magnus

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/94 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/00012

摘要： Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

公开(公告)号：US09281286B1

公开(公告)日：2016-03-08

申请号：US14470679

申请日：2014-08-27

申请人： Weng F. Yap ,  Alan J. Magnus

发明人： Weng F. Yap ,  Alan J. Magnus

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/03 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/03466 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014

摘要： Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.

摘要翻译： 提供了微电子封装和用于制造具有纹理化焊盘的微电子封装的方法，其可以提高焊点可靠性。 在一个实施例中，该方法包括在下焊盘电介质层中形成具有纹理图案（例如阴影图案）的纹理化电介质区域。 在纹理化电介质区域上产生纹理化的焊盘。 纹理化焊料焊盘具有焊接接触表面，纹理图案被转印到该焊接接触表面，使得焊料接触表面的面积相对于等效尺寸的非变形焊料垫而增加。

公开(公告)号：US09401339B2

公开(公告)日：2016-07-26

申请号：US14277343

申请日：2014-05-14

申请人： Weng F. Yap ,  Alan J. Magnus

发明人： Weng F. Yap ,  Alan J. Magnus

IPC分类号： H01L23/52 ,  H01L23/00 ,  B23K1/20 ,  B23K1/00 ,  H01L23/31 ,  B23K3/06

CPC分类号： H01L24/20 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/02166 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13016 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/0132

摘要： Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

摘要翻译： 提供了晶圆级封装以及用于生产具有不可润湿的焊锡圈的晶片级封装的方法。 在一个实施例中，该方法包括在暴露焊料掩模层下面的图案化金属层的区域的焊料掩模层中形成焊接掩模开口。 在焊料掩模层中形成焊接掩模开口之前或之后，产生部分地在图案化金属层的暴露区域上延伸的不可润湿的焊接套环。 将焊球沉积在不可润湿的焊接环上并进入焊接掩模开口中，使得周边间隙设置在限定焊料掩模开口的焊料球的基部和焊料掩模层的侧壁周围。

公开(公告)号：US20130207255A1

公开(公告)日：2013-08-15

申请号：US13397034

申请日：2012-02-15

申请人： Alan J. Magnus ,  Carl E.D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

发明人： Alan J. Magnus ,  Carl E.D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

IPC分类号： H01L21/60 ,  H01L23/34 ,  H01L21/56

CPC分类号： H01L23/36 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

摘要翻译： 提供了一种用于形成用于封装在半导体器件封装中的管芯的用于形成用于电和/或热的背面接触的方法和设备。 可以在半导体器件封装内容纳不同厚度的管芯。 本发明的实施例提供耦合到管芯的背面接触的导电基座，其中在将管芯封装在封装内之前执行耦合。 此外，耦合到半导体器件封装内的不同裸片的导电基座具有这样的厚度，使得每个导电基座可以暴露在封装的背面，而不会暴露或损坏任何封装的裸片的背面。 本发明的实施例提供了导电基座由导电或导热材料制成并且使用导电和/或导热粘合剂耦合到器件裸片接触。

公开(公告)号：US08685790B2

公开(公告)日：2014-04-01

申请号：US13397034

申请日：2012-02-15

申请人： Alan J. Magnus ,  Carl E. D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

发明人： Alan J. Magnus ,  Carl E. D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

IPC分类号： H01L21/00

CPC分类号： H01L23/36 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

摘要翻译： 提供了一种用于形成用于封装在半导体器件封装中的管芯的用于形成用于电和/或热的背面接触的方法和设备。 可以在半导体器件封装内容纳不同厚度的管芯。 本发明的实施例提供耦合到管芯的背面接触的导电基座，其中在将管芯封装在封装内之前执行耦合。 此外，耦合到半导体器件封装内的不同裸片的导电基座具有这样的厚度，使得每个导电基座可以暴露在封装的背面，而不会暴露或损坏任何封装的裸片的背面。 本发明的实施例提供了导电基座由导电或导热材料制成并且使用导电和/或导热粘合剂耦合到器件裸片接触。

公开(公告)号：US07892950B2

公开(公告)日：2011-02-22

申请号：US12432540

申请日：2009-04-29

申请人： Alan J. Magnus ,  Justin E. Poarch ,  Jason R. Wright

发明人： Alan J. Magnus ,  Justin E. Poarch ,  Jason R. Wright

IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01016 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).

摘要翻译： 在半导体器件（52）制造过程中用于处理面板（26,128）的方法（20,104）需要在面板（26,128）的表面（34,132）中形成与一个 用于面板（26,128）的切割图案（54）。 凹槽（72,142）部分地延伸通过面板（26,128），使得面板（26,128）保持完整。 凹槽（72,142）减轻面板（26,128）中的应力以减小面板（26,128）翘曲，从而使面板（26,128）可靠地保持在支撑结构（88,98,138 ）经历进一步处理时的真空，例如焊料印刷（86）。 根据切割图案（54），方法（20,104）还需要通过面板（26,128）从表面（34,132）切割（96,152），同时面板（26,128）是 安装在支撑结构（98,138）上以使半导体器件（52）单数化。

公开(公告)号：US20100279467A1

公开(公告)日：2010-11-04

申请号：US12432540

申请日：2009-04-29

申请人： Alan J. Magnus ,  Justin E. Poarch ,  Jason R. Wright

发明人： Alan J. Magnus ,  Justin E. Poarch ,  Jason R. Wright

IPC分类号： H01L21/50 ,  H01L21/302

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01016 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).

摘要翻译： 在半导体器件（52）制造过程中用于处理面板（26,128）的方法（20,104）需要在面板（26,128）的表面（34,132）中形成与一个 用于面板（26,128）的切割图案（54）。 凹槽（72,142）部分地延伸通过面板（26,128），使得面板（26,128）保持完整。 凹槽（72,142）减轻面板（26,128）中的应力以减小面板（26,128）翘曲，从而使面板（26,128）可靠地保持在支撑结构（88,98,138 ）经历进一步处理时的真空，例如焊料印刷（86）。 根据切割图案（54），方法（20,104）还需要通过面板（26,128）从表面（34,132）切割（96,152），同时面板（26,128）是 安装在支撑结构（98,138）上以使半导体器件（52）单数化。