公开(公告)号：US09331029B2

公开(公告)日：2016-05-03

申请号：US14210057

申请日：2014-03-13

申请人： Michael B. Vincent ,  Zhiwei Gong ,  Jason R. Wright

发明人： Michael B. Vincent ,  Zhiwei Gong ,  Jason R. Wright

IPC分类号： H01L21/44 ,  H01L23/66 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/498 ,  H01L23/532

CPC分类号： H01L23/66 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49883 ,  H01L23/5328 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32153 ,  H01L2224/32221 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105

摘要： Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

摘要翻译： 提供了制造微电子封装的方法，例如扇出晶片级封装和微电子封装。 在一个实施例中，该方法包括将第一半导体管芯放置在临时衬底上，形成与第一半导体管芯和临时衬底中的至少一个接触的导电迹线，以及封装第一半导体管芯和导电 在模制面板内追踪。 去除临时衬底以露出模制面板的前侧，电导体迹线至少部分地暴露在模制面板的前侧。 在模制面板的前侧形成至少一个再分布层，所述至少一个再分配层包括与导电迹线欧姆接触的互连线。

公开(公告)号：US09142434B2

公开(公告)日：2015-09-22

申请号：US13125502

申请日：2008-10-23

申请人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

发明人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/67092 ,  H01L21/568 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68322 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

摘要翻译： 提供了形成电子组件的方法。 提供具有嵌入其中的多个电子部件的器件基板。 使用粘合剂材料将装置基板附接到载体基板。 通过器件基板形成多个切口，以将器件基板分成多个部分。 多个部分中的每一个包括至少一个电子部件。 在远离载体基板的方向上对多个部分中的每一个施加力以从载体基板移除多个部分。

公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US20130320530A1

公开(公告)日：2013-12-05

申请号：US13483064

申请日：2012-05-30

申请人： Dominic Poh Meng Koey ,  Zhiwei Gong

发明人： Dominic Poh Meng Koey ,  Zhiwei Gong

IPC分类号： H01L21/56 ,  H01L23/485

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices.

摘要翻译： 通过在半导体管芯之间和之外定位具有金属接地平面构件阵列的半导体管芯阵列来组装表面贴装半导体器件。 模具阵列和接地平面构件被封装在模塑料中。 在模具和接地平面构件阵列上形成再分布层。 再分配层在绝缘材料层内具有一组再分布导体。 再分布导体将模具的电触点与器件的外部电接触元件互连。 随着多个装置同时形成，相邻的装置通过沿模具之间的锯条切割而分离（分割）。 模制化合物插入在接地平面构件的连接杆之间以及在锯道中的再分配层的绝缘材料以及分割装置的侧表面处。

公开(公告)号：US20130127030A1

公开(公告)日：2013-05-23

申请号：US13299564

申请日：2011-11-18

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/4853 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

摘要翻译： 提供了一种在封装封装之前在半导体器件封装中形成通孔的方法。 通过在具有互连焊盘的印刷电路基板上的光刻和金属沉积形成一个或多个信号导管。 在去除光致抗蚀材料之后，通过封装信号导管以及任何半导体管芯，引线接合以及封装的其它部分来构建半导体器件封装。 每个信号管道的自由端被暴露，并且信号管道用作通孔，以在从顶部安装的封装到印刷电路衬底互连件的连接和半导体管芯或封装触头的电触点之间提供信号承载路径。 使用该方法，信号导管可以以印刷电路基板上的各种几何布置提供，以包含在半导体器件封装中。 还提供了结合预制通孔的半导体器件封装。

公开(公告)号：US20130049217A1

公开(公告)日：2013-02-28

申请号：US13222143

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Jason R. Wright

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Jason R. Wright

IPC分类号： H01L21/768 ,  H01L23/538

CPC分类号： H01L23/49827 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 将一个或多个信号导管放置在随后嵌入封装的半导体器件封装中的保持器中。 信号管道的端部暴露，然后将信号导管用作通过封装通孔，在封装的底部和顶部上的互连或触点之间提供信号承载通路。 取决于应用的性质，可以提供各种几何形状和材料的支架。 此外，具有信号导管的多个保持器可以提供在单个封装中，以在例如系统级封装应用中提供更复杂的互连配置要求。

公开(公告)号：US09064977B2

公开(公告)日：2015-06-23

申请号：US13591990

申请日：2012-08-22

申请人： Zhiwei Gong (Tony) ,  Michael B Vincent ,  Scott M Hayes ,  Jason R Wright

发明人： Zhiwei Gong (Tony) ,  Michael B Vincent ,  Scott M Hayes ,  Jason R Wright

IPC分类号： H01L29/72 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L25/03

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括产生部分完成的叠层微电子封装，其包括具有垂直封装侧壁的封装体，嵌入封装主体内的多个微电子器件，以及电耦合到多个微电子器件的封装边缘导体， 垂直封装侧壁。 可流动的导电材料施加在垂直封装侧壁上，并与封装边缘导体接触。 然后去除可流动导电材料的选定部分，以至少部分地限定电隔离的侧壁导体，其电耦合到不同的封装边缘导体。

公开(公告)号：US08980696B2

公开(公告)日：2015-03-17

申请号：US13292103

申请日：2011-11-09

申请人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V. C. Muniandy ,  Weng Foong Yap

发明人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V. C. Muniandy ,  Weng Foong Yap

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  A01J21/00 ,  A01J25/12 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

摘要： A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

摘要翻译： 封装半导体管芯的方法包括使用嵌入式接地层或嵌入式嵌入式单元。 嵌入式单元是具有至少一个空腔的单个独立单元。 嵌入式单元被放置在过程安装表面的封装区域内和之内。 嵌入式单元可以具有不同的尺寸和形状以及在处理半导体管芯期间可以放置在基板，面板或带上的预定位置的多个不同的空腔，该半导体管芯嵌入到再分布芯片封装（RCP）或晶片级封装 WFL）面板。 嵌入式单元提供功能和设计灵活性，可以在单个处理面板或批次中运行多个嵌入式单元和半导体管芯或具有不同尺寸和尺寸的部件，并减少封装和封装后固化期间的管芯漂移，移动或歪斜。

公开(公告)号：US08916421B2

公开(公告)日：2014-12-23

申请号：US13222148

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L21/70 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 一个或多个信号管道耦合到引线框架，引线框架随后嵌入在封装的半导体器件封装中。 信号管道的自由端被暴露，而另一端保持联接到引线框架。 然后，信号导管用作通过封装通孔，在封装的底部和顶部与引线之间的互连或接触之间提供信号承载通路。

公开(公告)号：US20140054797A1

公开(公告)日：2014-02-27

申请号：US13591990

申请日：2012-08-22

申请人： Zhiwei Gong (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

发明人： Zhiwei Gong (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括产生部分完成的叠层微电子封装，其包括具有垂直封装侧壁的封装体，嵌入封装主体内的多个微电子器件，以及电耦合到多个微电子器件的封装边缘导体， 垂直封装侧壁。 可流动的导电材料施加在垂直封装侧壁上，并与封装边缘导体接触。 然后去除可流动导电材料的选定部分，以至少部分地限定电隔离的侧壁导体，其电耦合到不同的封装边缘导体。