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1.发明申请SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING 有权具有背面接触的半导体器件封装和制造方法公开(公告)号：US20130207255A1
公开(公告)日：2013-08-15
申请号：US13397034
申请日：2012-02-15
CPC分类号： H01L23/36 , H01L21/568 , H01L23/3128 , H01L23/3677 , H01L23/4334 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/96 , H01L2224/0401 , H01L2224/04026 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/83815 , H01L2224/83851 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2924/12042 , H01L2924/1301 , H01L2924/13034 , H01L2924/181 , H01L2224/83 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2924/00
摘要： A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.
摘要翻译： 提供了一种用于形成用于封装在半导体器件封装中的管芯的用于形成用于电和/或热的背面接触的方法和设备。 可以在半导体器件封装内容纳不同厚度的管芯。 本发明的实施例提供耦合到管芯的背面接触的导电基座，其中在将管芯封装在封装内之前执行耦合。 此外，耦合到半导体器件封装内的不同裸片的导电基座具有这样的厚度，使得每个导电基座可以暴露在封装的背面，而不会暴露或损坏任何封装的裸片的背面。 本发明的实施例提供了导电基座由导电或导热材料制成并且使用导电和/或导热粘合剂耦合到器件裸片接触。
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2.发明授权Semiconductor device package having backside contact and method for manufacturing 有权具有背面接触的半导体器件封装和制造方法公开(公告)号：US08685790B2
公开(公告)日：2014-04-01
申请号：US13397034
申请日：2012-02-15
IPC分类号： H01L21/00
CPC分类号： H01L23/36 , H01L21/568 , H01L23/3128 , H01L23/3677 , H01L23/4334 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/96 , H01L2224/0401 , H01L2224/04026 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/83815 , H01L2224/83851 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2924/12042 , H01L2924/1301 , H01L2924/13034 , H01L2924/181 , H01L2224/83 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2924/00
摘要： A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.
摘要翻译： 提供了一种用于形成用于封装在半导体器件封装中的管芯的用于形成用于电和/或热的背面接触的方法和设备。 可以在半导体器件封装内容纳不同厚度的管芯。 本发明的实施例提供耦合到管芯的背面接触的导电基座，其中在将管芯封装在封装内之前执行耦合。 此外，耦合到半导体器件封装内的不同裸片的导电基座具有这样的厚度，使得每个导电基座可以暴露在封装的背面，而不会暴露或损坏任何封装的裸片的背面。 本发明的实施例提供了导电基座由导电或导热材料制成并且使用导电和/或导热粘合剂耦合到器件裸片接触。
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3.发明申请公开(公告)号：US20100279467A1
公开(公告)日：2010-11-04
申请号：US12432540
申请日：2009-04-29
IPC分类号： H01L21/50 , H01L21/302
CPC分类号： H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01016 , H01L2924/01033 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3511 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).
摘要翻译： 在半导体器件（52）制造过程中用于处理面板（26,128）的方法（20,104）需要在面板（26,128）的表面（34,132）中形成与一个 用于面板（26,128）的切割图案（54）。 凹槽（72,142）部分地延伸通过面板（26,128），使得面板（26,128）保持完整。 凹槽（72,142）减轻面板（26,128）中的应力以减小面板（26,128）翘曲，从而使面板（26,128）可靠地保持在支撑结构（88,98,138 ）经历进一步处理时的真空，例如焊料印刷（86）。 根据切割图案（54），方法（20,104）还需要通过面板（26,128）从表面（34,132）切割（96,152），同时面板（26,128）是 安装在支撑结构（98,138）上以使半导体器件（52）单数化。
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公开(公告)号：US08841758B2
公开(公告)日：2014-09-23
申请号：US13537392
申请日：2012-06-29
IPC分类号： H01L23/495
CPC分类号： H01L23/49537 , H01L21/4842 , H01L23/3107 , H01L23/3114 , H01L23/49541 , H01L23/49548 , H01L23/49558 , H01L23/49586 , H01L24/97 , H01L2924/181 , Y10T29/49121 , H01L2924/00
摘要： A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.
摘要翻译： 一种用于提高组装在引线框架（112）中的集成电路封装（140）的锯切质量和润湿性的结构和方法，所述引线框架（112）在引线中具有半蚀刻凹槽（134）。 形成半导体器件封装的方法包括提供具有多个引线框架的引线框条（110）。 引导框架中的每一个包括在分割条带之前至少部分地填充有材料（400）的凹陷（130）。
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5.发明授权公开(公告)号：US07892950B2
公开(公告)日：2011-02-22
申请号：US12432540
申请日：2009-04-29
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01016 , H01L2924/01033 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3511 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).
摘要翻译： 在半导体器件（52）制造过程中用于处理面板（26,128）的方法（20,104）需要在面板（26,128）的表面（34,132）中形成与一个 用于面板（26,128）的切割图案（54）。 凹槽（72,142）部分地延伸通过面板（26,128），使得面板（26,128）保持完整。 凹槽（72,142）减轻面板（26,128）中的应力以减小面板（26,128）翘曲，从而使面板（26,128）可靠地保持在支撑结构（88,98,138 ）经历进一步处理时的真空，例如焊料印刷（86）。 根据切割图案（54），方法（20,104）还需要通过面板（26,128）从表面（34,132）切割（96,152），同时面板（26,128）是 安装在支撑结构（98,138）上以使半导体器件（52）单数化。
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公开(公告)号：US07132303B2
公开(公告)日：2006-11-07
申请号：US10739605
申请日：2003-12-18
申请人： James J. Wang , Alan J. Magnus , Justin E. Poarch
发明人： James J. Wang , Alan J. Magnus , Justin E. Poarch
IPC分类号： H01L21/00
CPC分类号： H01L24/10 , H01L22/32 , H01L24/13 , H01L24/81 , H01L24/94 , H01L2224/13 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/48247 , H01L2224/48465 , H01L2224/81011 , H01L2224/81801 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012
摘要： One embodiment relates to using a robust metal layer of a semiconductor device to form landing pads. In one embodiment, a sputterable, nonwettable refractory metal is used as a solder mask for the landing pads. A second device may then be coupled to the robust metal layer landing pads of the semiconductor device. In one embodiment, the landing pads are formed while the semiconductor device is in wafer form, and a second device is then coupled to the landing pads of each of the plurality of semiconductor devices within the wafer, such that each semiconductor device within the wafer is electrically coupled to a second device. In this manner, each semiconductor device within the wafer and its corresponding second device may be probed and tested as a system. After probing and testing, the wafer may be singulated into a plurality of individual device assemblies which may then be packaged.
摘要翻译： 一个实施例涉及使用半导体器件的坚固的金属层来形成着陆焊盘。 在一个实施例中，使用可溅射的不可润湿的难熔金属作为着陆焊盘的焊接掩模。 然后可以将第二器件耦合到半导体器件的坚固的金属层着陆焊盘。 在一个实施例中，在半导体器件处于晶片形式的同时形成着陆焊盘，然后将第二器件耦合到晶片内的多个半导体器件的每个的着陆焊盘，使得晶片内的每个半导体器件 电耦合到第二装置。 以这种方式，可以将晶片内的每个半导体器件及其对应的第二器件作为系统进行探测和测试。 在探测和测试之后，晶片可以被分成多个单独的器件组件，然后可以将其封装。
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7.发明授权公开(公告)号：US07868729B2
公开(公告)日：2011-01-11
申请号：US12397112
申请日：2009-03-03
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F17/04 , H01F27/2804 , H01F2017/002 , H01F2027/2814 , H01L23/645 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/0557 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/1134 , H01L2224/13144 , H01L2224/32145 , H01L2224/73204 , H01L2224/81011 , H01L2224/81012 , H01L2224/81013 , H01L2224/81203 , H01L2224/81801 , H01L2224/97 , H01L2225/06527 , H01L2225/06586 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/07802 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , Y10T29/4902 , Y10T29/49117 , H01L2224/81 , H01L2924/00 , H01L2924/00014
摘要： A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).
摘要翻译： 层叠的半导体器件组件（20）包括其中形成有导电迹线（34）的器件（24）和电连接到导电迹线（34）的导电互连（28）。 另一个装置（26）具有形成在其中的导电迹线（44）和形成在装置（26）的外表面（52）上的装置焊盘（54）。 方法（120）需要将磁芯（84）附接到装置（24）的外表面（42）上，并且使用螺柱（92）在外表面（42）上形成（92）导电互连件（28） 使得互连（28）围绕磁芯（30）的凸起技术。 使用热压接将导电互连（28）与器件焊盘（54）耦合（126），以将器件（26）与器件（24）耦合以形成围绕磁芯（30）缠绕的连续器件线圈（22） ）从导线（34），导电互连（28）和迹线（44）的交替电连接。
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8.发明申请公开(公告)号：US20100225434A1
公开(公告)日：2010-09-09
申请号：US12397112
申请日：2009-03-03
CPC分类号： H01F17/0013 , H01F17/04 , H01F27/2804 , H01F2017/002 , H01F2027/2814 , H01L23/645 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/0557 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/1134 , H01L2224/13144 , H01L2224/32145 , H01L2224/73204 , H01L2224/81011 , H01L2224/81012 , H01L2224/81013 , H01L2224/81203 , H01L2224/81801 , H01L2224/97 , H01L2225/06527 , H01L2225/06586 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/07802 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , Y10T29/4902 , Y10T29/49117 , H01L2224/81 , H01L2924/00 , H01L2924/00014
摘要： A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).
摘要翻译： 层叠的半导体器件组件（20）包括其中形成有导电迹线（34）的器件（24）和电连接到导电迹线（34）的导电互连（28）。 另一个装置（26）具有形成在其中的导电迹线（44）和形成在装置（26）的外表面（52）上的装置焊盘（54）。 方法（120）需要将磁芯（84）附接到装置（24）的外表面（42）上，并且使用螺柱（92）在外表面（42）上形成（92）导电互连件（28） 使得互连（28）围绕磁芯（30）的凸起技术。 使用热压接将导电互连（28）与器件焊盘（54）耦合（126），以将器件（26）与器件（24）耦合以形成围绕磁芯（30）缠绕的连续器件线圈（22） ）从导线（34），导电互连（28）和迹线（44）的交替电连接。
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9.发明授权Multi-chips semiconductor device assemblies and methods for fabricating the same 有权多芯片半导体器件组件及其制造方法公开(公告)号：US07339275B2
公开(公告)日：2008-03-04
申请号：US10995818
申请日：2004-11-22
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/73 , H01L25/0652 , H01L2224/16145 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48247 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06527 , H01L2225/06555 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/00012 , H01L2924/00
摘要： Multi-chip semiconductor device assemblies and methods for fabricating such assemblies are provided. An exemplary assembly comprises a first chip having a first surface and comprising a plurality of conductive pads disposed at the first surface and a plurality of circuits. Each of the pads is electrically coupled to one of the circuits. A second chip having a second surface is disposed adjacent to the first surface of the first chip. The second chip comprises a plurality of bonding members disposed at the second surface. Each of the bonding members is connected to a corresponding pad. The second chip is electrically coupled to at least one of the circuits via a corresponding pad and a corresponding bonding member. The second chip comprises a first and a second portion. The first portion overlies at least a portion of the first chip and the second portion extends beyond the first chip.
摘要翻译： 提供了多芯片半导体器件组件及其制造方法。 示例性组件包括具有第一表面并且包括设置在第一表面处的多个导电焊盘的第一芯片和多个电路。 每个焊盘电耦合到一个电路。 具有第二表面的第二芯片设置成与第一芯片的第一表面相邻。 第二芯片包括设置在第二表面处的多个接合部件。 每个接合构件连接到相应的垫。 第二芯片通过相应的焊盘和相应的焊接部件电耦合到至少一个电路。 第二芯片包括第一和第二部分。 第一部分覆盖第一芯片的至少一部分，并且第二部分延伸超过第一芯片。
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