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    SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE
    5.
    发明申请
    SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE 有权
    集成电子放电器件的半导体器件

    公开(公告)号：US20110089540A1

    公开(公告)日：2011-04-21

    申请号：US12580658

    申请日：2009-10-16

    申请人： Robert J. Drost ,  Robert D. Hopkins ,  Alex Chow

    发明人： Robert J. Drost ,  Robert D. Hopkins ,  Alex Chow

    IPC分类号： H01L23/60

    CPC分类号： H01L23/60 ,  H01L24/05 ,  H01L27/0288 ,  H01L2224/02166 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

    摘要： A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

    摘要翻译： 描述半导体管芯。 该半导体管芯包括具有耦合到输入 - 输出（I / O）焊盘的金属部件并且经由信号线耦合到接地电压的静电放电（ESD）器件。 此外，金属部件和I / O焊盘的相邻边缘分开限定ESD间隙的间隔。 当场发射或电离电流流过ESD间隙时，金属部件为瞬态ESD信号提供到接地电压的放电路径。 此外，ESD间隙至少部分封闭，使得在ESD间隙中存在气体。

    CAPACITIVELY AND CONDUCTIVELY COUPLED MULTIPLEXER
    6.
    发明申请
    CAPACITIVELY AND CONDUCTIVELY COUPLED MULTIPLEXER 有权
    电容式和导体耦合多路复用器

    公开(公告)号：US20100176878A1

    公开(公告)日：2010-07-15

    申请号：US12352481

    申请日：2009-01-12

    申请人： Robert J. Drost ,  Alex Chow ,  Robert D. Hopkins

    发明人： Robert J. Drost ,  Alex Chow ,  Robert D. Hopkins

    IPC分类号： H03F1/50

    CPC分类号： H03K17/005 ,  H03K17/693

    摘要： A capacitively and conductively coupled multiplexer (C3mux) circuit is described. This C3mux circuit includes a set of nonlinear coupling capacitors, such as metal-oxide-semiconductor (MOS) transistors, that can multiplex multiple input signals while minimizing the parasitic capacitance penalty associated with the ‘off’ paths. In particular, the capacitance of a given MOS transistor depends on whether its channel is present or absent. Furthermore, this channel is formed based on whether the gate-to-source and drain voltages for the MOS transistor are greater than the MOS transistor's threshold voltage. Note that the capacitance of the MOS transistors in the C3mux circuit is low for the unselected inputs. Consequently, the parasitic loading and the delay increase slowly as a function of the number of inputs. Moreover, the conductive feedback can be used to maintain a DC level of the input signals.

    摘要翻译： 描述了电容和导电耦合多路复用器（C3mux）电路。 该C3mux电路包括一组非线性耦合电容器，例如金属氧化物半导体（MOS）晶体管，其可以复用多个输入信号，同时最小化与“关闭”路径相关联的寄生电容损耗。 特别地，给定MOS晶体管的电容取决于其通道是存在还是不存在。 此外，该沟道是基于MOS晶体管的栅极 - 源极和漏极电压是否大于MOS晶体管的阈值电压而形成的。 请注意，C3mux电路中的MOS晶体管的电容对于未选择的输入为低电平。 因此，寄生负载和延迟作为输入数量的函数缓慢增加。 此外，导电反馈可用于维持输入信号的直流电平。

    SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE
    7.
    发明申请
    SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE 有权
    集成电子放电器件的半导体器件

    公开(公告)号：US20120229941A1

    公开(公告)日：2012-09-13

    申请号：US13473479

    申请日：2012-05-16

    申请人： Robert J. Drost ,  Robert D. Hopkins ,  Alex Chow

    发明人： Robert J. Drost ,  Robert D. Hopkins ,  Alex Chow

    IPC分类号： H02H9/04

    CPC分类号： H01L23/60 ,  H01L24/05 ,  H01L27/0288 ,  H01L2224/02166 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

    摘要： A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

    摘要翻译： 描述半导体管芯。 该半导体管芯包括具有耦合到输入 - 输出（I / O）焊盘的金属部件并且经由信号线耦合到接地电压的静电放电（ESD）器件。 此外，金属部件和I / O焊盘的相邻边缘分开限定ESD间隙的间隔。 当场发射或电离电流流过ESD间隙时，金属部件为瞬态ESD信号提供到接地电压的放电路径。 此外，ESD间隙至少部分封闭，使得在ESD间隙中存在气体。

    ACTIVE RESISTOR USED IN A FEEDBACK AMPLIFIER PARTICULARLY USEFUL FOR PROXIMITY COMMUNICATION
    9.
    发明申请
    ACTIVE RESISTOR USED IN A FEEDBACK AMPLIFIER PARTICULARLY USEFUL FOR PROXIMITY COMMUNICATION 有权
    在反馈放大器中使用的有源电阻特别适用于接近通信

    公开(公告)号：US20090315624A1

    公开(公告)日：2009-12-24

    申请号：US12143991

    申请日：2008-06-23

    申请人： Alex Chow ,  Robert J. Drost ,  Robert D. Hopkins

    发明人： Alex Chow ,  Robert J. Drost ,  Robert D. Hopkins

    IPC分类号： H03F1/38

    CPC分类号： H03F1/34 ,  H03F2200/141

    摘要： An active resistor and its use in a negative feedback amplifier allow wide voltage swings on the input and output signals. One embodiment includes parallel pass-gate MOS transistors of opposite conductivity types connected between the input and output nodes. Bootstrapping transistors are connected between the gates of the pass-gate transistors and respective bias voltages. Coupling capacitors are connected between the gates and the output node. Additional coupling capacitors may be connected between the gates and the input node to make the resistor symmetric. In other embodiments, only one pass-gate transistor is used.

    摘要翻译： 有源电阻及其在负反馈放大器中的应用允许输入和输出信号上的宽电压摆幅。 一个实施例包括连接在输入和输出节点之间的相反导电类型的并行栅极MOS晶体管。 自举晶体管连接在通栅晶体管的栅极和相应的偏置电压之间。 耦合电容器连接在门和输出节点之间。 附加耦合电容器可以连接在栅极和输入节点之间，以使电阻器对称。 在其它实施例中，仅使用一个栅极晶体管。