公开(公告)号：US6122284A

公开(公告)日：2000-09-19

申请号：US889109

申请日：1997-07-07

申请人： Ali Tasdighi ,  Joseph J. Judkins, III ,  Chuong Nguyen ,  Donald E. Alfano

发明人： Ali Tasdighi ,  Joseph J. Judkins, III ,  Chuong Nguyen ,  Donald E. Alfano

IPC分类号： H04Q11/00

CPC分类号： H04Q11/04

摘要： In the preferred embodiment, the outputs of a plurality of analog signal generators are connected to a single wire (the analog bus). Each analog signal generator is addressable by a unique code provided to its respective address input terminals. A host controller selectively addresses only one of the analog signal generators such that an output of only one of the analog signal generators is applied to the analog bus at a time. In this manner, a single wire may be used to transmit a plurality of analog signals to a receiver. In one embodiment, the receiver is a MUX having an output connected to an ADC.

摘要翻译： 在优选实施例中，多个模拟信号发生器的输出端连接到单线（模拟总线）。 每个模拟信号发生器可通过提供给其相应地址输入端的唯一代码寻址。 主机控制器仅选择性地仅寻址模拟信号发生器中的一个，使得仅一个模拟信号发生器的输出一次被施加到模拟总线。 以这种方式，可以使用单根线将多个模拟信号发送到接收机。 在一个实施例中，接收器是具有连接到ADC的输出的MUX。

公开(公告)号：US6054823A

公开(公告)日：2000-04-25

申请号：US81309

申请日：1998-05-19

申请人： Jerry Collings ,  Chuong Nguyen ,  Joseph James Judkins, III ,  Donald E. Alfano ,  Ali Tasdighi ,  Quoi V. Huynh ,  Sang T. Ngo

发明人： Jerry Collings ,  Chuong Nguyen ,  Joseph James Judkins, III ,  Donald E. Alfano ,  Ali Tasdighi ,  Quoi V. Huynh ,  Sang T. Ngo

IPC分类号： F04D27/02 ,  H02H7/093 ,  H01R39/46

CPC分类号： H02H7/093 ,  F04D27/008

摘要： An apparatus for sensing the rotation of a brushless DC fan includes the fan and a sense/driver circuit and a capacitance. The sense/driver circuit is coupled to the fan to receive a sense input signal including a fluctuating electrical effect caused by fan commutation events. The sense/driver circuit processes the sense input signal to generate a sense output signal indicative of fan operation. The sense/driver circuit includes an integrated circuit. The integrated circuit includes a sense input pin, a ground return pin, a driver circuit, an integrated filter portion, a filter pin and a level detecting circuit. The capacitance is coupled to the filter pin to provide a filter with the integrated filter portion. The driver circuit includes a control terminal, a first current handling terminal coupled to the sense input pin and a second current handling terminal coupled to provide a ground return pat. The integrated filter portion includes a filter input coupled to at least one of the first and second current handling terminals of the driver circuit, and a filter output for providing a filter output signal to the level detecting circuit. The level detecting circuit generates the sense output signal from the filter output signal. The filter derives the filter output signal indicative of the fan commutation events responsive to receiving a signal at the sense input pin.

摘要翻译： 用于感测无刷直流风扇的旋转的装置包括风扇和感测/驱动器电路和电容。 感测/驱动器电路耦合到风扇以接收包括由风扇换向事件引起的波动电效应的感测输入信号。 感测/驱动电路处理感测输入信号以产生指示风扇操作的感测输出信号。 感测/驱动电路包括集成电路。 集成电路包括感测输入引脚，接地返回引脚，驱动器电路，集成滤波器部分，滤波器引脚和电平检测电路。 电容耦合到滤波器引脚以提供具有集成滤波器部分的滤波器。 驱动器电路包括控制端子，耦合到感测输入引脚的第一电流处理端子和耦合以提供接地回路的第二电流处理端子。 集成滤波器部分包括耦合到驱动器电路的第一和第二电流处理终端中的至少一个的滤波器输入和用于向电平检测电路提供滤波器输出信号的滤波器输出。 电平检测电路从滤波器输出信号产生感测输出信号。 响应于在感测输入引脚处接收到信号，滤波器导出指示风扇换向事件的滤波器输出信号。

公开(公告)号：US6037732A

公开(公告)日：2000-03-14

申请号：US63072

申请日：1998-04-21

申请人： Donald E. Alfano ,  Joseph J. Judkins, III ,  Quoi V. Huynh ,  Sang T. Ngo

发明人： Donald E. Alfano ,  Joseph J. Judkins, III ,  Quoi V. Huynh ,  Sang T. Ngo

IPC分类号： G05D23/19 ,  G05B5/00

CPC分类号： G05D23/1912 ,  Y10S388/903

摘要： A method for controlling the operation of a brushless DC fan for cooling heat generating components of a system is provided. The method includes providing a system temperature signal indicative of a system temperature and providing an intelligent shutdown enable signal. The system temperature signal is compared with a shutdown temperature signal if the intelligent shutdown enable signal has a first value. The shutdown temperature signal is representative of a shutdown temperature value. The fan is operated at a generally temperature proportional speed after comparing the system temperature signal with the shutdown temperature signal if the system temperature as indicated by the system temperature signal is greater than the shutdown temperature value as indicated by the shutdown temperature signal. A shutdown mode is entered by the fan after comparing the system temperature signal with the shutdown temperature signal if the system temperature as indicated by the system temperature signal is less than the shutdown temperature value as indicated by the shutdown temperature signal. The system temperature signal is compared with the shutdown temperature signal after entering the shutdown mode by the fan. Operation of the fan is initiated if the system temperature as indicated by the system temperature signal is greater than the shutdown temperature value as indicated by the shutdown temperature signal and the fan is in the shutdown mode.

摘要翻译： 提供了一种用于控制用于冷却系统的发热部件的无刷DC风扇的操作的方法。 该方法包括提供指示系统温度并提供智能关机使能信号的系统温度信号。 如果智能关机使能信号具有第一值，则将系统温度信号与停机温度信号进行比较。 停机温度信号代表关机温度值。 如果由系统温度信号指示的系统温度大于关闭温度信号所指示的关机温度值，则将系统温度信号与停机温度信号进行比较后，风扇以大致温度比例速度运行。 如果系统温度信号指示的系统温度低于关机温度信号所示的关机温度值，则将风扇信号与关机温度信号进行比较后，风扇进入关机模式。 系统温度信号与风扇进入关机模式后的关机温度信号进行比较。 如系统温度信号所示的系统温度大于关机温度信号所示的关机温度值，风扇处于关机模式，则开始运行风扇。

公开(公告)号：US07738568B2

公开(公告)日：2010-06-15

申请号：US11772162

申请日：2007-06-30

申请人： Donald E. Alfano ,  Brett Etter ,  Timothy Dupuis

发明人： Donald E. Alfano ,  Brett Etter ,  Timothy Dupuis

IPC分类号： H04B3/00

CPC分类号： H01L23/66 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1204 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H04B3/542 ,  H04B3/548 ,  H04B3/56 ,  H04B2203/542 ,  H04L25/0266 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A system for providing multiple communication channels over a single voltage isolation link includes first circuitry for multiplexing a plurality of digital data inputs from a plurality of communication channels onto the single voltage isolation link. Second circuitry de-multiplexes the plurality of digital data inputs from the single voltage isolation link to the plurality of communication channels. An RF isolator is used for providing the single voltage isolation link.

摘要翻译： 用于在单个电压隔离链路上提供多个通信信道的系统包括用于将来自多个通信信道的多个数字数据输入复用到单电压隔离链路上的第一电路。 第二电路将多个数字数据输入从单电压隔离链路解复用到多个通信信道。 RF隔离器用于提供单电压隔离链路。

公开(公告)号：US07660968B2

公开(公告)日：2010-02-09

申请号：US11772184

申请日：2007-06-30

申请人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

发明人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC分类号： G06F13/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

摘要翻译： 可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。 这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。 该功能包括作为输入的功能的输出，功能定义的功能。 每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。 可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。 可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。 提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

公开(公告)号：US07640455B2

公开(公告)日：2009-12-29

申请号：US11172482

申请日：2005-06-30

申请人： Ka Y. Leung ,  Kafai Leung ,  Donald E. Alfano

发明人： Ka Y. Leung ,  Kafai Leung ,  Donald E. Alfano

IPC分类号： G06F11/00

CPC分类号： H02M3/33515 ,  H02M3/157 ,  H02M2001/0012 ,  H02M2001/007

摘要： An apparatus for forcing outputs of a digital controller of a switching power converter to a safe state during shutdown of the switching power converter is described. The apparatus includes a multiplexer providing an output signal of the digital controller and having a first input of the multiplexer connected to receive a switching control signal control signal from the digital controller. The multiplexer also has a plurality of inputs from control registers providing programmed safe state values. The multiplexer connects one of the first input or the inputs from the plurality of control registers to the output of the multiplexer responsive to a multiplexer control signal. Control logic generates the multiplexer control signal responsive to at least one of an end of frame interrupt, an over current interrupt, an enable interrupt or a software bypass signal.

摘要翻译： 描述了用于在切换功率转换器关闭期间将开关电源转换器的数字控制器的输出强制到安全状态的装置。 该装置包括多路复用器，提供数字控制器的输出信号，并具有多路复用器的第一输入端，用于从数字控制器接收切换控制信号控制信号。 复用器还具有提供编程的安全状态值的来自控制寄存器的多个输入。 多路复用器响应于多路复用器控制信号将来自多个控制寄存器的第一输入或输入中的一个连接到多路复用器的输出。 响应于帧中断，过电流中断，使能中断或软件旁路信号中的至少一个，控制逻辑产生多路复用器控制信号。

公开(公告)号：US07577223B2

公开(公告)日：2009-08-18

申请号：US11772186

申请日：2007-06-30

申请人： Donald E. Alfano ,  Brett Etter ,  Timothy Dupuis

发明人： Donald E. Alfano ,  Brett Etter ,  Timothy Dupuis

IPC分类号： H04L7/04

CPC分类号： H01L23/66 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1204 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H04B3/542 ,  H04B3/56 ,  H04B2203/542 ,  H04L25/0266 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry. The first circuitry is operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input data pins across the first communications channel and to communicate the synchronization clock signal across the second communications channel. The second circuitry is operable to receive the communicated data from the first circuitry and reconstruct the data for output on the ones of the plurality of output data pins corresponding to the two or more of the associated plurality of input data pins from which the data was communicated responsive to the synchronization clock signal.

摘要翻译： 一种用于在电压隔离屏障上提供数字数据信号的数据传输的集成电路隔离器包括：集成电路封装，其具有在隔离屏障的一侧上的第一多个输入数据引脚和在另一侧的相应的多个输出数据引脚 隔离边界。 第一电路与第一组多个输入数据引脚相关联，第二电路与多个输出数据引脚相关联。 通信接口在电压隔离屏障上提供用于将数据从第一电路传送到第二电路的第一通信信道和用于将同步时钟数据从第一电路传送到第二电路的第二通信信道。 第一电路可操作以从时间上彼此重叠的输入数字数据传送信息，并在第一通信信道上的相关联的第一多个输入数据引脚中的两个或更多个上接收信号，并且跨越第二通信信道传送同步时钟信号。 第二电路可操作以从第一电路接收所传送的数据，并且重构数据以输出与多个输入数据引脚相对应的多个输出数据引脚中的两个或多个相关联的多个输入数据引脚，数据从其传送 响应于同步时钟信号。

公开(公告)号：US07446430B2

公开(公告)日：2008-11-04

申请号：US11394909

申请日：2006-03-31

申请人： Kafai Leung ,  Ka Y. Leung ,  Donald E. Alfano

发明人： Kafai Leung ,  Ka Y. Leung ,  Donald E. Alfano

IPC分类号： H02J1/00

CPC分类号： H02J13/0062 ,  H02J1/08 ,  H02J13/0003 ,  H02M3/33515 ,  H02M3/33576 ,  H02M2001/008 ,  H03K3/356121 ,  H03K3/35613 ,  H03K7/08 ,  H03M1/363 ,  Y10T307/461 ,  Y10T307/469

摘要： A distributed power system for delivering DC power to a plurality of loads. A plurality of power converter modules having associated therewith a DC/DC power conversion operation are provided, each disposed proximate an associated one of the loads, each of said converter modules having associated therewith a switching pulse generator for generating switching pulses. A distributed power line distributes input power to each of the modules. A data communication line distributes command data between the modules. Each of the modules includes a power regulation section for receiving the input power to generate a DC output by controlling the operation of the switching pulse generator. It also includes a processing section for interfacing with the data communication line for interfacing with the commands, the processing function operating in at least a slave mode to receive commands from the data communication bus. At least one of the modules operates in both a slave mode and a master mode. In the master mode, the processing section generates commands for transmission over the data communication line to an addressed one of the other of the modules and internally for use in the local slave mode of operation. The processing section in the slave mode of operation is operable to configure and monitor the operation of the power regulation section.

摘要翻译： 一种用于将DC电力传送到多个负载的分布式电力系统。 提供了具有与其相关联的DC / DC功率转换操作的多个功率转换器模块，每个功率转换器模块设置在相关联的一个负载附近，每个所述转换器模块具有与其相关联的用于产生开关脉冲的开关脉冲发生器。 分布式电力线将输入电力分配给每个模块。 数据通信线路在模块之间分配命令数据。 每个模块包括功率调节部分，用于通过控制开关脉冲发生器的操作来接收输入功率以产生DC输出。 它还包括一个处理部分，用于与数据通信线对接，用于与命令进行接口，处理功能以至少从属模式操作，以从数据通信总线接收命令。 至少一个模块在从模式和主模式下都工作。 在主模式下，处理部分生成用于通过数据通信线路发送到另一个模块中寻址的另一个模块的命令，并在内部生成用于本地从属操作模式的命令。 在从属操作模式下的处理部分可操作以配置和监视功率调节部分的操作。

公开(公告)号：US07171542B1

公开(公告)日：2007-01-30

申请号：US09885459

申请日：2001-06-19

申请人： Donald E. Alfano ,  Danny Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R Holberg

发明人： Donald E. Alfano ,  Danny Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R Holberg

IPC分类号： G06F13/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

摘要翻译： 集成电路中的可重构处理器系统包括对一组指令进行操作以执行预定义的处理的处理器核心。 提供多个输入/输出引脚用于与外部信号进行接口。 可重新配置的接口通过多个功能块中的选择的接口在处理器核心和输入/输出引脚之间进行接口。 可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心与处理器核心相连接的功能。 功能块提供处理器内核与输入/输出引脚的接口。

公开(公告)号：US08861229B2

公开(公告)日：2014-10-14

申请号：US12129039

申请日：2008-05-29

申请人： Donald E. Alfano ,  Timothy J. Dupuis ,  Zhiwei Dong ,  Brett E. Etter

发明人： Donald E. Alfano ,  Timothy J. Dupuis ,  Zhiwei Dong ,  Brett E. Etter

IPC分类号： H02M3/335 ,  H02M3/156

CPC分类号： H03K17/691 ,  H03K17/7955

摘要： An apparatus includes a regulator circuit that generates a voltage in response to an input current being supplied to an input terminal and functional circuitry, powered by the voltage generated by the regulator circuit. The functional circuitry, e.g., an oscillator, generates a signal using the generated voltage, the signal indicative that the current is being supplied to the apparatus. The signal can be provided over an isolation link to provide a control signal for controlling a high voltage driver circuit.

摘要翻译： 一种装置包括调节器电路，其响应于输入电流产生电压，该输入电流被提供给由调节器电路产生的电压供电的输入端子和功能电路。 功能电路，例如振荡器，使用所产生的电压产生信号，该信号指示电流被提供给设备。 信号可以通过隔离链路提供，以提供用于控制高电压驱动器电路的控制信号。