公开(公告)号：US08735291B2

公开(公告)日：2014-05-27

申请号：US13217489

申请日：2011-08-25

申请人： Alok Ranjan ,  Akiteru Ko

发明人： Alok Ranjan ,  Akiteru Ko

IPC分类号： H01L21/302

CPC分类号： H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

摘要： A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

摘要翻译： 描述了在基板上构图栅叠层的方法。 该方法包括在衬底上准备栅极堆叠，其中栅极堆叠包括形成在高k层上的高k层和栅极层。 该方法还包括使用脉冲偏置等离子体蚀刻工艺将形成在栅极层中的图案转移到高k层，以及选择用于脉冲偏压等离子体蚀刻工艺的工艺条件，以实现在衬底中形成的具有深度 小于2纳米（nm）。

公开(公告)号：US08809194B2

公开(公告)日：2014-08-19

申请号：US13413915

申请日：2012-03-07

申请人： Alok Ranjan ,  Kaushik Arun Kumar

发明人： Alok Ranjan ,  Kaushik Arun Kumar

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L21/0337 ,  H01J37/32082 ,  H01J2237/334 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/6656 ,  Y10S438/947 ,  Y10S438/976

摘要： A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.

摘要翻译： 描述了用于执行间隔物蚀刻工艺的方法。 该方法包括在衬底上的栅极结构上保形地施加间隔物材料，并且执行间隔物蚀刻工艺顺序以从栅极结构和衬底部分去除间隔物材料，同时保持沿栅极结构的侧壁定位的侧壁间隔物 。 间隔物蚀刻工艺序列可以包括在间隔物材料的暴露表面上沉积含SiOCl的层以形成间隔物保护层。

公开(公告)号：US20130252430A1

公开(公告)日：2013-09-26

申请号：US13589096

申请日：2012-08-18

申请人： Alok Ranjan ,  Angelique D. Raley

发明人： Alok Ranjan ,  Angelique D. Raley

IPC分类号： H01L21/311

CPC分类号： H01L21/0206 ,  H01J37/32082 ,  H01J2237/334 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.

摘要翻译： 描述了用于执行间隔物蚀刻工艺的方法。 该方法包括在基板上提供栅极结构，该栅极结构具有保形施加在栅极结构上的低k间隔物材料，并且执行间隔物蚀刻工艺序列以从栅极结构和衬底部分去除间隔物材料，同时保持侧壁间隔物 沿着门结构的侧壁定位。 间隔物蚀刻工艺序列可以包括在所述间隔物材料的暴露表面上沉积隔离物保护层，并且执行一个或多个蚀刻工艺以选择性地和各向异性地去除间隔物保护层和间隔物材料以留在侧壁上的侧壁间隔物 其中，当通过一个或多个蚀刻工艺部分或完全地消耗时，间隔物保护层在组成和/或介电常数上表现出减小的变化。

公开(公告)号：US08592327B2

公开(公告)日：2013-11-26

申请号：US13413878

申请日：2012-03-07

申请人： Alok Ranjan ,  Kaushik Arun Kumar

发明人： Alok Ranjan ,  Kaushik Arun Kumar

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814 ,  H01L2221/1063

摘要： A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.

摘要翻译： 描述了一种用于保护暴露的低k表面的方法。 该方法包括接收具有掩模层和形成在其上的低k层的衬底，其中使用光刻工艺在掩模层中形成的图案已经使用蚀刻工艺转移到低k层，以在其中形成结构特征 。 此外，该方法包括在掩模层和低k层的暴露表面上形成含SiOCl的层，并且从掩模层的顶表面和结构特征的底表面各向异性除去含SiOCl层 同时在结构特征的侧壁表面上保留含SiOCl层的剩余部分。 该方法还包括进行灰化处理以除去掩模层，然后从结构特征的侧壁表面选择性地除去含SiOCl层的剩余部分。

公开(公告)号：US09111746B2

公开(公告)日：2015-08-18

申请号：US13589096

申请日：2012-08-18

申请人： Alok Ranjan ,  Angelique D. Raley

发明人： Alok Ranjan ,  Angelique D. Raley

IPC分类号： H01L21/302 ,  H01L29/76 ,  H01L21/02 ,  H01L21/311 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01J37/32

CPC分类号： H01L21/0206 ,  H01J37/32082 ,  H01J2237/334 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.

摘要翻译： 描述了用于执行间隔物蚀刻工艺的方法。 该方法包括在基板上提供栅极结构，该栅极结构具有保形施加在栅极结构上的低k间隔物材料，并且执行间隔物蚀刻工艺序列以从栅极结构和衬底部分去除间隔物材料，同时保持侧壁间隔物 沿着门结构的侧壁定位。 间隔物蚀刻工艺序列可以包括在所述间隔物材料的暴露表面上沉积隔离物保护层，并且执行一个或多个蚀刻工艺以选择性地和各向异性地去除间隔物保护层和间隔物材料以留在侧壁上的侧壁间隔物 其中，当通过一个或多个蚀刻工艺部分或完全地消耗时，间隔物保护层在组成和/或介电常数上表现出减小的变化。

公开(公告)号：US08551877B2

公开(公告)日：2013-10-08

申请号：US13414015

申请日：2012-03-07

申请人： Alok Ranjan ,  Kaushik Arun Kumar

发明人： Alok Ranjan ,  Kaushik Arun Kumar

IPC分类号： H01L21/4763 ,  H01L23/532

CPC分类号： H01L21/76811 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

摘要： A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.

摘要翻译： 描述了用于去除硬掩模的方法的方法。 该方法包括使用一个或多个蚀刻工艺和覆盖低k绝缘层的硬掩模层，在衬底上的低k绝缘层中形成沟槽通孔结构的至少一部分。 此后，该方法包括在沟槽通孔结构的暴露表面上沉积含SiOCl的层以形成绝缘保护层，执行一个或多个蚀刻工艺以使至少一部分含SiOCl层从至少一个 沟槽通孔结构的表面，并且使用掩模去除蚀刻工艺去除硬掩模层。