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    Methods of Processing Semiconductor Wafers Having Silicon Carbide Power Devices Thereon
    2.
    发明申请
    Methods of Processing Semiconductor Wafers Having Silicon Carbide Power Devices Thereon 有权
    处理具有碳化硅功率器件的半导体晶片的方法

    公开(公告)号：US20090233418A1

    公开(公告)日：2009-09-17

    申请号：US12474720

    申请日：2009-05-29

    申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  Matthew Donofrio

    发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  Matthew Donofrio

    IPC分类号： H01L21/304

    CPC分类号： H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L29/6606 ,  Y10S438/931

    摘要： Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

    摘要翻译： 公开了形成碳化硅半导体器件的方法。 所述方法包括在具有第一厚度的碳化硅衬底的第一表面上形成半导体器件，以及将载体衬底安装到碳化硅衬底的第一表面上。 载体衬底为碳化硅衬底提供机械支撑。 所述方法还包括将碳化硅衬底减薄至小于第一厚度的厚度，在与碳化硅衬底的第一表面相对的稀薄的碳化硅衬底上形成金属层，并局部退火金属层以在其上形成欧姆接触 薄碳化硅衬底与碳化硅衬底的第一表面相对。 将碳化硅衬底分离以提供单片半导体器件。

    Methods of processing semiconductor wafers having silicon carbide power devices thereon
    3.
    发明授权
    Methods of processing semiconductor wafers having silicon carbide power devices thereon 有权
    处理其上具有碳化硅功率器件的半导体晶片的方法

    公开(公告)号：US07547578B2

    公开(公告)日：2009-06-16

    申请号：US11531975

    申请日：2006-09-14

    申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  Matthew Donofrio

    发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  Matthew Donofrio

    IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L29/6606 ,  Y10S438/931

    摘要： Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

    摘要翻译： 公开了形成碳化硅半导体器件的方法。 所述方法包括在具有第一厚度的碳化硅衬底的第一表面上形成半导体器件，以及将载体衬底安装到碳化硅衬底的第一表面上。 载体衬底为碳化硅衬底提供机械支撑。 所述方法还包括将碳化硅衬底减薄至小于第一厚度的厚度，在与碳化硅衬底的第一表面相对的稀薄的碳化硅衬底上形成金属层，并局部退火金属层以在其上形成欧姆接触 薄碳化硅衬底与碳化硅衬底的第一表面相对。 将碳化硅衬底分离以提供单片半导体器件。

    METHODS OF PROCESSING SEMICONDUCTOR WAFERS HAVING SILICON CARBIDE POWER DEVICES THEREON
    4.
    发明申请
    METHODS OF PROCESSING SEMICONDUCTOR WAFERS HAVING SILICON CARBIDE POWER DEVICES THEREON 有权
    加工具有硅碳膜电源器件的半导体晶体管的方法

    公开(公告)号：US20070066039A1

    公开(公告)日：2007-03-22

    申请号：US11531975

    申请日：2006-09-14

    申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  Matthew Donofrio

    发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  Matthew Donofrio

    IPC分类号： H01L21/425

    CPC分类号： H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L29/6606 ,  Y10S438/931

    摘要： Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

    摘要翻译： 公开了形成碳化硅半导体器件的方法。 所述方法包括在具有第一厚度的碳化硅衬底的第一表面上形成半导体器件，以及将载体衬底安装到碳化硅衬底的第一表面上。 载体衬底为碳化硅衬底提供机械支撑。 所述方法还包括将碳化硅衬底减薄至小于第一厚度的厚度，在与碳化硅衬底的第一表面相对的稀薄的碳化硅衬底上形成金属层，并局部退火金属层以在其上形成欧姆接触 薄碳化硅衬底与碳化硅衬底的第一表面相对。 将碳化硅衬底分离以提供单片半导体器件。

    Power switching semiconductor devices including rectifying junction-shunts
    7.
    发明授权
    Power switching semiconductor devices including rectifying junction-shunts 有权
    功率开关半导体器件包括整流结分路

    公开(公告)号：US08546874B2

    公开(公告)日：2013-10-01

    申请号：US13267966

    申请日：2011-10-07

    申请人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

    发明人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7803 ,  H01L21/0465 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861

    摘要： A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.

    摘要翻译： 半导体器件包括漂移层和与漂移层形成p-n结的体区。 接触器区域在体区域中，并且分流通道区域从接触器区域延伸穿过体区域到漂移层。 分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于 内部电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区域和体区之间的pn结的电压是不导通的。

    SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL
    10.
    发明申请
    SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL 有权
    具有高阻塞电压的SIC器件由负极水平端接

    公开(公告)号：US20120292636A1

    公开(公告)日：2012-11-22

    申请号：US13108366

    申请日：2011-05-16

    申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    IPC分类号： H01L29/161

    CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

    摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

    摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。