公开(公告)号：US6123825A

公开(公告)日：2000-09-26

申请号：US203926

申请日：1998-12-02

申请人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

发明人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

IPC分类号： H01L21/3205 ,  C25D5/10 ,  C25D7/00 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  C23C28/00 ,  C23C28/02 ,  C25D5/02 ,  C25D5/34 ,  C25D5/50

CPC分类号： C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12646 ,  Y10T428/1291

摘要： An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.

摘要翻译： 一种抗电镀铜膜结构和形成该结构的方法。 膜结构含有高杂质含量，耐晶粒生长，具有优良的冶金，热机械和电学性能。 该方法包括以下步骤：（a）至少间接地在基底上提供种子层，籽晶层具有暴露表面; （b）将基板浸入电镀液中; （c）在种子层的暴露表面上电沉积含铜膜，所述含铜膜具有第一表面; （d）将所述基板保持在所述电镀液中的浸渍状态; （e）将另外的含铜膜从所述电镀溶液电沉积到所述第一表面上; （f）从电镀液中除去基板; 和（g）干燥基材。

公开(公告)号：US06768203B1

公开(公告)日：2004-07-27

申请号：US09262690

申请日：1999-03-04

申请人： Andrew H. Simon ,  Cyprian E. Uzoh

发明人： Andrew H. Simon ,  Cyprian E. Uzoh

IPC分类号： H01L2348

CPC分类号： H01L21/76844 ,  H01L21/76865 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to a method of forming a bottomless liner structure. The method involves the steps of first obtaining a material having a via. Next, a first layer is deposited on the material, the first layer covering the sidewalls and bottom of the via. Finally, a second layer is sputter deposited on the first material, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

摘要翻译： 本发明涉及一种形成无底衬管结构的方法。 该方法包括首先获得具有通孔的材料的步骤。 接下来，第一层沉积在材料上，第一层覆盖通孔的侧壁和底部。 最后，第二层被溅射沉积在第一材料上，材料Rf在第二层被溅射沉积的至少一部分时间内偏置，使得沉积在通孔底部上的第一层被基本上去除并且基本上被除去 沉积在通孔侧壁上的所有第一层都不受影响。

公开(公告)号：US06569783B2

公开(公告)日：2003-05-27

申请号：US10036476

申请日：2002-01-07

申请人： Cyprian E. Uzoh ,  Daniel C. Edelstein ,  Andrew H. Simon

发明人： Cyprian E. Uzoh ,  Daniel C. Edelstein ,  Andrew H. Simon

IPC分类号： H01L2100

CPC分类号： H01L21/76846 ,  C23C14/0084 ,  C23C14/06 ,  H01L23/53223 ,  H01L23/53257 ,  H01L2221/1078 ,  H01L2924/0002 ,  Y10S257/915 ,  Y10T428/24942 ,  Y10T428/30 ,  Y10T428/31678 ,  H01L2924/00

摘要： A barrier film for a semiconductor device structure. The barrier film includes a compound including nitrogen and at least one of titanium or tantalum, nitrogen in a concentration that varies within the barrier film, and oxygen in a concentration that varies within the barrier film.

公开(公告)号：US06337151B1

公开(公告)日：2002-01-08

申请号：US09377330

申请日：1999-08-18

申请人： Cyprian E. Uzoh ,  Daniel C. Edelstein ,  Andrew H. Simon

发明人： Cyprian E. Uzoh ,  Daniel C. Edelstein ,  Andrew H. Simon

IPC分类号： H01L2300

CPC分类号： H01L21/76846 ,  C23C14/0084 ,  C23C14/06 ,  H01L23/53223 ,  H01L23/53257 ,  H01L2221/1078 ,  H01L2924/0002 ,  Y10S257/915 ,  Y10T428/24942 ,  Y10T428/30 ,  Y10T428/31678 ,  H01L2924/00

摘要： A barrier film for a semiconductor device structure. The barrier film includes a compound including nitrogen and at least one of titanium or tantalum, nitrogen in a concentration that varies within the barrier film, and oxygen in a concentration that varies within the barrier film.

摘要翻译： 一种用于半导体器件结构的阻挡膜。 阻挡膜包括包括氮和钛或钽中的至少一种的化合物，在阻挡膜内变化的浓度的氮和在阻挡膜内变化的浓度的氧。

公开(公告)号：US06572982B1

公开(公告)日：2003-06-03

申请号：US09604539

申请日：2000-06-27

申请人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

发明人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

IPC分类号： B32B1504

CPC分类号： C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12646 ,  Y10T428/1291

摘要： An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.

摘要翻译： 一种抗电镀铜膜结构和形成该结构的方法。 膜结构含有高杂质含量，耐晶粒生长，具有优良的冶金，热机械和电学性能。 该方法包括以下步骤：（a）至少间接地在基底上提供种子层，籽晶层具有暴露表面; （b）将基板浸入电镀液中; （c）在种子层的暴露表面上电沉积含铜膜，所述含铜膜具有第一表面; （d）将所述基板保持在所述电镀液中的浸渍状态; （e）将另外的含铜膜从所述电镀溶液电沉积到所述第一表面上; （f）从电镀液中除去基板; 和（g）干燥基材。

公开(公告)号：US5933753A

公开(公告)日：1999-08-03

申请号：US767572

申请日：1996-12-16

申请人： Andrew H. Simon ,  Cyprian E. Uzoh

发明人： Andrew H. Simon ,  Cyprian E. Uzoh

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76865 ,  H01L21/76873 ,  H01L2924/0002

摘要： This invention relates to a method of forming a bottomless liner structure. The method involves the steps of first obtaining a material having a via. Next, a first layer is deposited on the material, the first layer covering the sidewalls and bottom of the via. Finally, a second layer is sputter deposited on the first material, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

摘要翻译： 本发明涉及一种形成无底衬管结构的方法。 该方法包括首先获得具有通孔的材料的步骤。 接下来，第一层沉积在材料上，第一层覆盖通孔的侧壁和底部。 最后，第二层被溅射沉积在第一材料上，材料Rf在第二层被溅射沉积的至少一部分时间内偏置，使得沉积在通孔底部上的第一层被基本上去除并且基本上被除去 沉积在通孔侧壁上的所有第一层都不受影响。

公开(公告)号：US09685404B2

公开(公告)日：2017-06-20

申请号：US13348011

申请日：2012-01-11

申请人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

发明人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L23/522 ,  H01H85/02

CPC分类号： H01L23/5256 ,  H01H2085/0275 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：US09059169B2

公开(公告)日：2015-06-16

申请号：US13165087

申请日：2011-06-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01L21/26 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/768 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

摘要翻译： 提供线后端的电熔丝结构（BEOL）互连和制造方法。 该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。 该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。 该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

公开(公告)号：US08912658B2

公开(公告)日：2014-12-16

申请号：US12915510

申请日：2010-10-29

申请人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

发明人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

摘要翻译： 一种改进的互连结构，其包括具有嵌入其中的导电特征的介电层，所述导电特征具有与介电层的第二顶表面基本共面的第一顶表面; 金属盖层直接位于第一顶表面上，其中金属盖层基本上不延伸到第二顶表面上; 位于所述第二顶表面上的第一电介质盖层，其中所述第一电介质盖层基本上不延伸到所述第一顶表面上，并且所述第一电介质盖层比所述金属盖层厚; 以及金属盖层和第一电介质盖层上的第二电介质盖层。 还提供了形成互连结构的方法。

公开(公告)号：US08232148B2

公开(公告)日：2012-07-31

申请号：US12717398

申请日：2010-03-04

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

IPC分类号： H01L21/00

CPC分类号： H01L23/485 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76283 ,  H01L21/76877 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

摘要翻译： 电气装置设置有具有第一栅极结构的p型半导体器件，其包括在半导体衬底的顶部上的栅极电介质，p型功函数金属层，由钛和铝构成的金属层，以及金属 填充铝。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。 层间电介质存在于半导体衬底上。 层间电介质包括到p型和n型半导体器件的源区和漏区的互连。 互连由钛和铝构成的金属层和由铝组成的金属填充物构成。 本公开还提供了形成上述结构的方法。