公开(公告)号：US20130049158A1

公开(公告)日：2013-02-28

申请号：US13220816

申请日：2011-08-30

申请人： Augustin J. Hong ,  Woo-Shik Jung ,  Jeehwan Kim ,  Jae-woong Nah ,  Devendra K. Sadana

发明人： Augustin J. Hong ,  Woo-Shik Jung ,  Jeehwan Kim ,  Jae-woong Nah ,  Devendra K. Sadana

IPC分类号： H01L31/0352 ,  B32B5/16 ,  H01L21/302 ,  H01L29/06 ,  B82Y99/00

CPC分类号： H01L31/035227 ,  C03C15/00 ,  C03C17/06 ,  C03C2218/34 ,  H01L31/022433 ,  H01L31/02363 ,  H01L31/035281 ,  H01L31/0376 ,  H01L31/0392 ,  H01L31/03921 ,  H01L31/03923 ,  H01L31/03925 ,  H01L31/056 ,  H01L31/075 ,  Y02E10/52 ,  Y02E10/541 ,  Y02E10/548 ,  Y10S438/945 ,  Y10S977/773 ,  Y10S977/779 ,  Y10T428/12014 ,  Y10T428/12069 ,  Y10T428/12076 ,  Y10T428/24479 ,  Y10T428/24488 ,  Y10T428/2982

摘要： Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.

公开(公告)号：US20140060628A1

公开(公告)日：2014-03-06

申请号：US13611047

申请日：2012-09-12

申请人： Augustin J. Hong ,  Jeehwan Kim ,  Jae-woong Nah ,  Devendra K. Sadana

发明人： Augustin J. Hong ,  Jeehwan Kim ,  Jae-woong Nah ,  Devendra K. Sadana

IPC分类号： H01L31/0236

CPC分类号： H01L31/02366 ,  C03C15/00 ,  C03C2218/34 ,  Y02E10/50

摘要： A substrate for photovoltaic device includes a textured surface formed from silicon-based material. The textured surface includes a plurality of cones uniformly distributed across the textured surface. The uniformly distributed cones are configured by etching from a top surface of the substrate using a self-assembled solder dot mask evaporated on the substrate prior to etching. The cones are uniformly distributed as a result of gettering a process chamber prior to forming the solder dot mask. The cones have a height/width ratio between about 1 to about 4, and the cones have a density between 108 to 109 cones/cm2.

摘要翻译： 用于光伏器件的衬底包括由硅基材料形成的纹理表面。 纹理表面包括均匀分布在纹理化表面上的多个锥体。 均匀分布的锥体通过在蚀刻之前使用在衬底上蒸发的自组装焊点掩模从衬底的顶表面进行蚀刻而配置。 由于在形成焊点掩模之前吸收处理室，锥体均匀分布。 锥体具有约1至约4之间的高度/宽度比，并且锥体具有在108至109锥/ cm 2之间的密度。

公开(公告)号：US08272120B2

公开(公告)日：2012-09-25

申请号：US13186815

申请日：2011-07-20

申请人： Peter A. Gruber ,  Jae-woong Nah

发明人： Peter A. Gruber ,  Jae-woong Nah

IPC分类号： B23P19/00

CPC分类号： H01L24/29 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/29006 ,  H01L2224/29015 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32013 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/41 ,  Y10T29/5313 ,  Y10T29/53178 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199

摘要： An apparatus for applying solder to semiconductor chips is provided that employs a plurality of apertured decals to define areas for engaging solder on a semiconductor chip. Each of the plurality of decals includes an upper, center and bottom layer having apertures present therethrough. The apparatus fills the apertures with solder. The upper and bottom layers of the apertured decals are removed to provide solder portions projecting from the center layer. The apparatus provides a station for applying an adhesive layer to the exposed surfaces of the center layer having the solder portions projecting therefrom. The apparatus includes a station for contacting the solder and adhesive to the semiconductor chip. The apparatus also includes a separating structure for detaching the portion of the center layer that is in contacting to the semiconductor chip through the solder.

摘要翻译： 提供了一种用于向半导体芯片施加焊料的装置，其采用多个有孔贴花来限定用于接合半导体芯片上的焊料的区域。 多个贴花中的每一个包括具有穿过其中的孔的上部，中心和底部层。 该装置用焊料填充孔。 去除多孔贴花的上层和底层以提供从中心层突出的焊接部分。 该装置提供了一种用于将粘合剂层施加到具有从其突出的焊料部分的中心层的暴露表面的工位。 该装置包括用于将焊料和粘合剂接触到半导体芯片的工位。 该装置还包括分离结构，用于通过焊料分离与半导体芯片接触的部分中心层。

公开(公告)号：US20110272450A1

公开(公告)日：2011-11-10

申请号：US13186815

申请日：2011-07-20

申请人： Peter A. Gruber ,  Jae-woong Nah

发明人： Peter A. Gruber ,  Jae-woong Nah

IPC分类号： B23K3/08 ,  B23K3/06

CPC分类号： H01L24/29 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/29006 ,  H01L2224/29015 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32013 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/41 ,  Y10T29/5313 ,  Y10T29/53178 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199

摘要： A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

公开(公告)号：US20110233762A1

公开(公告)日：2011-09-29

申请号：US12731793

申请日：2010-03-25

申请人： Peter A. Gruber ,  Jae-woong Nah

发明人： Peter A. Gruber ,  Jae-woong Nah

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/563 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/29006 ,  H01L2224/29015 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32013 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

摘要翻译： 晶圆级集成互连贴花制造方法和晶圆级集成互连贴片布置。 根据关于集成电路和基板的焊接的技术，特别是提供焊接贴花方法的形成和利用，在本实例中，使用由固体膜材料构成的底部填充材料，其被施加在半导体芯片和 衬底，以提高倒装芯片封装的可靠性。 特别地，底部填充材料增加了受控的崩溃芯片连接（C4）凸点的耐疲劳性。