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    Relaxation Oscillator
    1.
    发明申请
    Relaxation Oscillator 有权
    放松振荡器

    公开(公告)号：US20140176250A1

    公开(公告)日：2014-06-26

    申请号：US13721885

    申请日：2012-12-20

    申请人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

    发明人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

    IPC分类号： H03K3/011

    CPC分类号： H03K3/0231

    摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.

    摘要翻译： 在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压 电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边沿，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

    Relaxation oscillator
    2.
    发明授权
    Relaxation oscillator 有权
    放松振荡器

    公开(公告)号：US09099994B2

    公开(公告)日：2015-08-04

    申请号：US13721885

    申请日：2012-12-20

    申请人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

    发明人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

    IPC分类号： H03K3/011 ,  H03K3/0231

    CPC分类号： H03K3/0231

    摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.

    摘要翻译： 在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压 电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边缘，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

    Digital to analog converter
    3.
    发明授权
    Digital to analog converter 有权
    数模转换器

    公开(公告)号：US08681026B2

    公开(公告)日：2014-03-25

    申请号：US13408173

    申请日：2012-02-29

    申请人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

    发明人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

    IPC分类号： H03M1/06

    CPC分类号： H03M1/1047 ,  H03M1/745 ,  H03M1/785

    摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

    摘要翻译： 使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值，以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，该模拟信号提供输入数字信号的模拟表示。

    DIGITAL TO ANALOG CONVERTER
    4.
    发明申请
    DIGITAL TO ANALOG CONVERTER 有权
    数字到模拟转换器

    公开(公告)号：US20130222162A1

    公开(公告)日：2013-08-29

    申请号：US13408173

    申请日：2012-02-29

    申请人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

    发明人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

    IPC分类号： H03M1/10 ,  H03M1/66

    CPC分类号： H03M1/1047 ,  H03M1/745 ,  H03M1/785

    摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

    摘要翻译： 使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值，以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，其提供输入数字信号的模拟表示。

    Successive approximation register analog-to-digital converter with multiple capacitive sampling circuits and method
    5.
    发明授权
    Successive approximation register analog-to-digital converter with multiple capacitive sampling circuits and method 有权
    具有多个电容采样电路和方法的逐次逼近寄存器模数转换器

    公开(公告)号：US08952839B2

    公开(公告)日：2015-02-10

    申请号：US13732113

    申请日：2012-12-31

    申请人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

    发明人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

    IPC分类号： H03M1/38 ,  H03K5/24 ,  H03M1/12 ,  H03M1/00 ,  H03M1/80 ,  H03M1/06

    CPC分类号： H03M1/38 ,  H03K5/24 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/466 ,  H03M1/804

    摘要： A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

    摘要翻译： 电路包括比较器，其包括第一输入端，第二输入端和输出端。 电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。 多个电容性采样电路中的每一个包括第一和第二电容器，并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。 多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合，以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。

    Successive Approximation Register Analog-to-Digital Converter with Multiple Capacitive Sampling Circuits and Method
    6.
    发明申请
    Successive Approximation Register Analog-to-Digital Converter with Multiple Capacitive Sampling Circuits and Method 有权
    具有多个电容采样电路的连续近似寄存器模数转换器和方法

    公开(公告)号：US20140184435A1

    公开(公告)日：2014-07-03

    申请号：US13732113

    申请日：2012-12-31

    申请人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

    发明人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

    IPC分类号： H03M1/38 ,  H03K5/24

    CPC分类号： H03M1/38 ,  H03K5/24 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/466 ,  H03M1/804

    摘要： A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

    摘要翻译： 电路包括比较器，其包括第一输入端，第二输入端和输出端。 电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。 多个电容性采样电路中的每一个包括第一和第二电容器，并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。 多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合，以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。

    DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS
    9.
    发明申请
    DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS 有权
    双循环架构可用于可编程时钟源和时钟多路复用器应用

    公开(公告)号：US20090039968A1

    公开(公告)日：2009-02-12

    申请号：US12249457

    申请日：2008-10-10

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    IPC分类号： H03L7/07

    CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

    摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

    Dual loop architecture useful for a programmable clock source and clock multiplier applications
    10.
    发明授权
    Dual loop architecture useful for a programmable clock source and clock multiplier applications 有权
    双循环架构可用于可编程时钟源和时钟乘法器应用

    公开(公告)号：US07436227B2

    公开(公告)日：2008-10-14

    申请号：US10878218

    申请日：2004-06-28

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    IPC分类号： H03L7/06

    CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

    摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。