公开(公告)号：US20120181672A1

公开(公告)日：2012-07-19

申请号：US13350520

申请日：2012-01-13

申请人： Bai-Yao LOU ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Tzu-Hsiang HUNG

发明人： Bai-Yao LOU ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Tzu-Hsiang HUNG

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/73153 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

公开(公告)号：US20120193786A1

公开(公告)日：2012-08-02

申请号：US13359452

申请日：2012-01-26

申请人： Chia-Sheng LIN ,  Tzu-Hsiang HUNG

发明人： Chia-Sheng LIN ,  Tzu-Hsiang HUNG

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L21/76898 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/522 ,  H01L23/60 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：衬底; 设置在所述基板中或所述基板上的器件区域; 信号焊盘，设置在所述衬底中或所述衬底上并电连接到所述器件区域; 设置在基板中或基板上的接地焊盘; 设置在所述基板的表面上的信号凸起，其中所述信号凸起通过信号传导层电连接到所述信号焊盘; 接地导电层，设置在所述基板的表面上并电连接到所述接地垫; 以及设置在基板的表面上的保护层，其中保护层完全覆盖信号传导层的整个侧面端子并且部分地覆盖接地导电层，使得接地导电层的侧端子暴露在 底物。

公开(公告)号：US20120056226A1

公开(公告)日：2012-03-08

申请号：US13224267

申请日：2011-09-01

申请人： Tzu-Hsiang HUNG ,  Hsin-Chih CHIU ,  Chuan-Jin SHIU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Yu-Min LIANG

发明人： Tzu-Hsiang HUNG ,  Hsin-Chih CHIU ,  Chuan-Jin SHIU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Yu-Min LIANG

IPC分类号： H01L33/58 ,  H01L31/0232

CPC分类号： H01L27/14618 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

公开(公告)号：US20120292744A1

公开(公告)日：2012-11-22

申请号：US13476748

申请日：2012-05-21

申请人： Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Po-Shen LIN

发明人： Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Po-Shen LIN

IPC分类号： H01L23/544 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L21/682 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：衬底，其中所述衬底从晶片切割; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及形成在所述绝缘层上的材料层，其中所述材料层具有识别标记，并且所述识别标记在从所述晶片切割所述基板之前，示出所述晶片中的所述基板的位置信息。

公开(公告)号：US20120205799A1

公开(公告)日：2012-08-16

申请号：US13369085

申请日：2012-02-08

申请人： Chia-Sheng LIN

发明人： Chia-Sheng LIN

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L31/02005 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02327 ,  H01L31/1876 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00

摘要： A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

摘要翻译： 公开了一种芯片封装。 所述封装包括具有第一表面和与其相对的第二表面的半导体芯片，与所述第一表面相邻的至少一个导电焊盘以及从所述第二表面向所述第一表面延伸以露出所述导电焊盘的开口。 与第一表面相邻的口径大于与第二表面相邻的开口的口径。 绝缘层和再分配层（RDL）依次设置在第二表面上并延伸到开口的侧壁和底部，RDL通过开口与导电焊盘电连接。 钝化层覆盖RDL并且部分填充开口以在开口中的钝化层和导电垫之间形成空隙。 还公开了芯片封装的制造方法。

公开(公告)号：US20110169159A1

公开(公告)日：2011-07-14

申请号：US12816301

申请日：2010-06-15

申请人： Chia-Sheng LIN ,  Po-Han Lee

发明人： Chia-Sheng LIN ,  Po-Han Lee

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L21/76898 ,  H01L21/481 ,  H01L21/76897 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00

摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

摘要翻译： 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。 形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。 然后，保护层设置在半导体衬底的第一表面和凹部中。