公开(公告)号：US20070105397A1

公开(公告)日：2007-05-10

申请号：US11593598

申请日：2006-11-07

Applicant: Jae-hwa Park ,  Woong-hee Sohn ,  Byung-hak Lee ,  Byung-hee Kim ,  Hee-seok Park

Inventor： Jae-hwa Park ,  Woong-hee Sohn ,  Byung-hak Lee ,  Byung-hee Kim ,  Hee-seok Park

IPC: H01L21/31

CPC classification number: B01J19/129 ,  B01J2219/0894 ,  H01L21/28185

Abstract: Embodiments of the invention provide a method for removing hydrogen gas from a chamber and a method for performing a semiconductor device fabrication sub-process and removing hydrogen gas from a chamber. The method for removing hydrogen gas from a chamber comprises removing a substrate from a chamber, wherein residual hydrogen gas is disposed in the chamber, injecting oxygen gas or ozone gas into the chamber, producing plasma in the chamber, and removing OH radicals from the chamber.

Abstract translation: 本发明的实施例提供了从室中除去氢气的方法以及用于执行半导体器件制造子过程并从室除去氢气的方法。 从室中除去氢气的方法包括从室中除去衬底，其中残留氢气设置在室中，将氧气或臭氧气体注入室中，在室中产生等离子体，并从室中除去OH自由基 。

公开(公告)号：US06391769B1

公开(公告)日：2002-05-21

申请号：US09525154

申请日：2000-03-14

Applicant: Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

Inventor： Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

IPC: H01L214763

CPC classification number: H01L21/76855 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

Abstract: A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.

Abstract translation: 一种用于形成填充高纵横比的接触孔或槽的金属互连的方法，以及由此制造的接触结构。 在半导体衬底上形成具有用作接触孔的凹陷区域，通孔或沟槽的电介质层图案。 在形成介电层图案的所得结构的整个表面上形成阻挡金属层。 仅在阻挡金属层的非凹陷区域选择性地形成抗成核层。 通过在除了凹陷区域之外的区域中形成覆盖阻挡金属层的金属层，然后在真空中自发氧化金属层，形成抗成核层。 此外，抗成核层可以通过原位形成阻挡金属层和金属层，然后通过退火处理来氧化金属层而形成。 随后，在由阻挡金属层包围的凹陷区域中选择性地形成金属插塞，从而形成用于完全填充接触孔或具有高纵横比的沟槽的金属互连。 可以形成金属衬垫而不是金属插塞，随后形成填充由金属衬垫包围的区域的金属层，从而形成用于完全填充具有高纵横比的接触孔或槽的金属互连。

公开(公告)号：US20120094437A1

公开(公告)日：2012-04-19

申请号：US13235717

申请日：2011-09-19

Applicant: Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Baek ,  Kyoung-hee Kim ,  Byung-lyul Park ,  Byung-hee Kim

Inventor： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Baek ,  Kyoung-hee Kim ,  Byung-lyul Park ,  Byung-hee Kim

IPC: H01L21/50 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract translation: 通过硅通孔（TSV）形成的方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k介电材料，通过蚀刻主通孔中的低k电介质形成次级通孔 以同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。 通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底表面形成，并且金属介电层形成在衬底的上表面上。 然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。

公开(公告)号：US07998810B2

公开(公告)日：2011-08-16

申请号：US12424922

申请日：2009-04-16

Applicant: Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

Inventor： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

Abstract: A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

Abstract translation: 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

公开(公告)号：US07968410B2

公开(公告)日：2011-06-28

申请号：US12460945

申请日：2009-07-27

Applicant: Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

Inventor： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

IPC: H01L21/336

CPC classification number: H01L27/11573 ,  H01L21/28123 ,  H01L21/28282

Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

Abstract translation: 一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

公开(公告)号：US20100240184A1

公开(公告)日：2010-09-23

申请号：US12626959

申请日：2009-11-30

Applicant: Eun-ji Jung ,  Hyun-soo Kim ,  Byung-hee Kim ,  Dae-yong Kim ,  Woong-hee Sohn ,  Kwang-jin Moon ,  Jang-hee Lee ,  Min-sang Song ,  Eun-ok Lee

Inventor： Eun-ji Jung ,  Hyun-soo Kim ,  Byung-hee Kim ,  Dae-yong Kim ,  Woong-hee Sohn ,  Kwang-jin Moon ,  Jang-hee Lee ,  Min-sang Song ,  Eun-ok Lee

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28052 ,  H01L29/4236

Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Abstract translation: 形成掩埋栅电极的方法防止在栅电极的硅化物层中形成空隙。 该方法开始于在半导体衬底中形成沟槽，在已经形成沟槽的半导体上形成共形栅极氧化层，在栅极氧化层上形成第一栅电极层，在第一栅电极上形成硅层 层填补沟槽。 然后，去除第一栅极电极层的一部分以形成暴露硅层的侧表面的一部分的凹部。 然后在包括硅层的半导体衬底上形成金属层。 接下来，半导体衬底退火，同时暴露硅层的侧表面以在硅层上形成金属硅化物层。

公开(公告)号：US07531459B2

公开(公告)日：2009-05-12

申请号：US11452042

申请日：2006-06-13

Applicant: Sug-woo Jung ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-ho Yun ,  Hyun-su Kim ,  Eun-ji Jung

Inventor： Sug-woo Jung ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-ho Yun ,  Hyun-su Kim ,  Eun-ji Jung

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.

Abstract translation: 形成金属硅化物层的方法可以包括在基板上形成金属层，并在第一温度下使用第一热处理在金属层上形成金属硅化物层。 然后在小于第一温度的第二温度下，在金属层上进行与第一热处理原位的第二工艺。

公开(公告)号：US07518214B2

公开(公告)日：2009-04-14

申请号：US11586610

申请日：2006-10-26

Applicant: Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

Inventor： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

IPC: H01L29/00

CPC classification number: H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

Abstract translation: 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

公开(公告)号：US06849555B2

公开(公告)日：2005-02-01

申请号：US10449522

申请日：2003-05-30

Applicant: Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

Inventor： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC: C23C14/56 ,  C23C16/44 ,  H01L21/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/302 ,  H01L21/461 ,  H01L21/677 ,  H01L21/768

CPC classification number: H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract translation: 提供了可用于形成具有多层结构的金属布线层和使用其的晶片处理方法的集成的原位簇型晶片处理装置。 晶片处理装置包括可以排出并具有多个闸阀的传送室，多个真空处理室，每个真空处理室可以经由一个闸阀连接到传送室;以及负载锁定室，其可以 被排出并且可连接到用于将氧基气体进料到负载锁定室中的第一气体供给管线。 在晶片处理方法中，在一个真空处理室中的晶片上形成预定层。 晶片上的预定层在负载锁定室或氧气氛室中被氧化。

公开(公告)号：US06697122B2

公开(公告)日：2004-02-24

申请号：US09790798

申请日：2001-02-23

Applicant: Byung-hee Kim

Inventor： Byung-hee Kim

IPC: H04N701

CPC classification number: H04N7/0135 ,  H04N7/012 ,  H04N9/641

Abstract: An apparatus for processing a signal in a digital television, and more particularly, an apparatus for adaptively processing an externally-input video signal in a digital television, in which a signal processing route is controlled to automatically determine the type of a video signal, which is input to an external input terminal, and to adaptively process the video signal regardless of whether the signal is an interlaced scanned video signal or a progressive scanned video signal, is provided. Accordingly, it is determined whether the externally input video signal is a 1H video signal or a 2H video signal, and signal processing is performed by deciding to use a signal processing route which is automatically adaptive to the video signal, thereby enabling the signal processing even in a case where a 2H video signal is input to the external input by determining the standard of the video signal input to the external input terminal, and performing signal processing which is automatically adaptive to the video signal.

Abstract translation: 一种用于处理数字电视中的信号的装置，更具体地，涉及一种用于自适应地处理数字电视中的外部输入视频信号的装置，其中信号处理路由被控制以自动确定视频信号的类型，其中 被输入到外部输入端子，并且自适应地处理视频信号，而不管该信号是隔行扫描视频信号还是逐行扫描视频信号。 因此，确定外部输入的视频信号是1H视频信号还是2H视频信号，并且通过决定使用自动适应于视频信号的信号处理路由来执行信号处理，从而使信号处理甚至可以 在通过确定输入到外部输入端子的视频信号的标准并且执行自动适应视频信号的信号处理将2H视频信号输入到外部输入的情况下。