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公开(公告)号：US08151012B2
公开(公告)日：2012-04-03
申请号：US12567638
申请日：2009-09-25
申请人： Changkyu Kim , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
发明人： Changkyu Kim , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
IPC分类号： G06F3/00
CPC分类号： G11C11/4082 , G06F1/3275 , G11C11/4085 , Y02D10/13 , Y02D10/14
摘要： Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
摘要翻译： 降低存储芯片能量消耗的方法，装置和系统，同时在执行任何工作负载的同时增加其效果带宽。 方法，设备和系统可以允许存储器芯片利用多个虚拟行缓冲器来响应包含在存储器阵列块中的数据的请求。 方法，装置和系统可以通过改变存储器阵列块和行缓冲器之间的数据传输大小来进一步消除或减少与将不需要的数据从存储器阵列块传送到行缓冲器相关联的成本。
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公开(公告)号：US20110078340A1
公开(公告)日：2011-03-31
申请号：US12567638
申请日：2009-09-25
申请人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
发明人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
CPC分类号： G11C11/4082 , G06F1/3275 , G11C11/4085 , Y02D10/13 , Y02D10/14
摘要： Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
摘要翻译： 降低存储芯片能量消耗的方法，装置和系统，同时在执行任何工作负载的同时增加其效果带宽。 方法，设备和系统可以允许存储器芯片利用多个虚拟行缓冲器来响应包含在存储器阵列块中的数据的请求。 方法，装置和系统可以通过改变存储器阵列块和行缓冲器之间的数据传输大小来进一步消除或减少与将不需要的数据从存储器阵列块传送到行缓冲器相关联的成本。
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公开(公告)号：US09791905B2
公开(公告)日：2017-10-17
申请号：US13995596
申请日：2011-10-28
CPC分类号： G06F1/26 , G06F1/266 , G06F1/3215 , G06F1/324 , G06F1/3265 , G06F1/3278 , G06F1/3296 , G06F13/14 , G09G5/006 , G09G5/18 , G09G2330/021 , Y02D10/126 , Y02D10/153 , Y02D10/157 , Y02D10/172 , Y02D50/20
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.
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公开(公告)号：US20160162434A1
公开(公告)日：2016-06-09
申请号：US14565176
申请日：2014-12-09
CPC分类号： G06F13/1657 , G06F11/10 , G06F13/4004 , G06F13/4022 , G06F13/4072 , G06F13/4217 , G06F13/4221 , G06F13/4234 , H04L25/4915 , Y02D10/14 , Y02D10/151
摘要： Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
摘要翻译： 动态总线反演（DBI）可编程级别为1和0的比例。 发送装置识别要发送的信号（“非反相信号”）的非反相版本中的1和0的数量和/或比率，以及信号的反转版本中的数字和/或比例的1和0“ 反转信号“）。 发送装置可以计算反相信号中的非反相信号中的1和0的差是否相同，或者反转信号中的1和0的差是否将计算的平均比值提升到更靠近目标比的1。 发送装置发送实现的信号，使所计算的平均比率更接近目标比率。
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5.发明授权Universal IO connector and interface capable of both wired and wireless operation 有权通用IO连接器和能够进行有线和无线操作的接口公开(公告)号：US09312908B2
公开(公告)日：2016-04-12
申请号：US13995592
申请日：2011-11-11
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
CPC分类号： H04B1/40 , G06F13/4068 , G06F2213/0042
摘要： Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.
摘要翻译： 互连设备的系统和方法可以包括具有基板，一组输入/输出（IO）触点，天线结构和收发器逻辑的连接器组件。 在一个示例中，收发器逻辑可以处理与天线结构相关联的一个或多个IO信号并且处理与该组IO触点相关联的一个或多个IO信号。
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公开(公告)号：US20140357128A1
公开(公告)日：2014-12-04
申请号：US13997096
申请日：2011-12-14
CPC分类号： H01R24/64 , H01R12/721 , H01R13/66 , H01R13/6658 , H01R24/28 , H01R24/62 , H01R2107/00
摘要： Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
摘要翻译： 方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。 衬底可以包括第一侧，第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。
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公开(公告)号：US20140197696A1
公开(公告)日：2014-07-17
申请号：US13995594
申请日：2011-10-17
CPC分类号： G06F13/385 , G06F1/266 , H01H9/54 , H01R13/6658 , Y10T307/74
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.
摘要翻译： 互连设备的系统和方法可以包括具有电压调节器，一个或多个信令电路，第一组触点，连接到一个或多个信号电路的第二组触点和逻辑电路的输入/输出（IO）连接器组件 接收配置命令。 如果配置命令对应于第一协议，逻辑还可以将第一组触点连接到电压调节器。 如果配置命令对应于第二协议，另一方面，逻辑可以将第一组联系人连接到一个或多个信令电路。
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公开(公告)号：US07710210B2
公开(公告)日：2010-05-04
申请号：US11905080
申请日：2007-09-27
IPC分类号： H03K3/282
CPC分类号： G01R31/31727 , G01R31/31726 , H03B5/1212 , H03B5/1228 , H03B5/1265 , H03B2200/0074 , H03L7/06 , H03L7/24 , H04L7/0008 , H04L7/0091 , H04L25/0272
摘要： An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.
摘要翻译： 提供一种包括注入锁定振荡器和发送装置的装置。 所述注入锁定振荡器接收第一时钟信号并通过使所述第一时钟信号偏移来提供第二时钟信号。 所述发送装置接收输入信号并接收所述第二时钟信号作为时钟信号，所述发送装置基于所接收的定时信号发送输出信号。
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公开(公告)号：US20080238503A1
公开(公告)日：2008-10-02
申请号：US11731776
申请日：2007-03-30
IPC分类号： H03L7/08
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译： 通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。 电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。 输出时钟是转发时钟的偏斜版本。
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公开(公告)号：US07164721B2
公开(公告)日：2007-01-16
申请号：US10326758
申请日：2002-12-20
申请人： James E. Jaussi , Bryan K. Casper
发明人： James E. Jaussi , Bryan K. Casper
CPC分类号： H04L25/028 , H04B3/03 , H04L5/1423 , H04L25/0272 , H04L25/0278 , H04L25/0292
摘要： According to some embodiments, a circuit is adapted to convert a first voltage signal from a bidirectional signal line to a first current signal, the first voltage signal to represent first data transmitted from a first transmitter and second data transmitted from a second transmitter. The circuit may be further operable to convert a second voltage signal to a second current signal, the second voltage signal, substantially to represent the first data, and to generate a first output signal to represent the second data based on the second current signal and the first current signal. Such a circuit might be an element of a simultaneous bidirectional signaling transceiver.
摘要翻译： 根据一些实施例，电路适于将来自双向信号线的第一电压信号转换为第一电流信号，第一电压信号表示从第一发送器发送的第一数据和从第二发送器发送的第二数据。 该电路还可以用于将第二电压信号转换成基本上表示第一数据的第二电压信号，第二电压信号，并且基于第二电流信号产生第一输出信号以表示第二数据， 第一个电流信号。 这样的电路可以是同时双向信令收发器的元件。
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