公开(公告)号：US4263709A

公开(公告)日：1981-04-28

申请号：US972410

申请日：1978-12-22

申请人： Charles E. Weitzel ,  Joseph H. Scott

发明人： Charles E. Weitzel ,  Joseph H. Scott

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  B01J17/00

CPC分类号： H01L29/6678 ,  H01L29/42384 ,  H01L29/78657

摘要： A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

摘要翻译： 半导体器件包括在半导体材料体的表面的一部分上的多晶硅区域。 一层氧化多晶硅也在半导体材料体上并延伸到多晶硅区域。 氧化硅层的表面与多晶硅区域的表面基本共面，从而可以容易地在半导体器件上设置金属膜导体。 多晶硅区域可以是MOS晶体管的栅极或任何类型的半导体器件的导电区域。 半导体器件通过在半导体材料体上形成多晶硅层，在多晶硅层的一部分上形成掩模，减小多晶硅层的未掩模部分的厚度，然后氧化多晶硅的未屏蔽部分 硅层形成氧化物层。

公开(公告)号：US4160260A

公开(公告)日：1979-07-03

申请号：US852565

申请日：1977-11-17

申请人： Charles E. Weitzel ,  Joseph H. Scott

发明人： Charles E. Weitzel ,  Joseph H. Scott

IPC分类号： H01L21/60 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L29/42384 ,  Y10S148/15

摘要： A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

公开(公告)号：US06893947B2

公开(公告)日：2005-05-17

申请号：US10179769

申请日：2002-06-25

申请人： Marino J. Martinez ,  Ernest Schirmann ,  Olin L. Hartin ,  Colby G. Rampley ,  Mariam G. Sadaka ,  Charles E. Weitzel ,  Julio Costa

发明人： Marino J. Martinez ,  Ernest Schirmann ,  Olin L. Hartin ,  Colby G. Rampley ,  Mariam G. Sadaka ,  Charles E. Weitzel ,  Julio Costa

IPC分类号： H01L21/285 ,  H01L21/337 ,  H01L29/80 ,  H01L21/22

CPC分类号： H01L29/66924 ,  H01L21/28587 ,  H01L29/802

摘要： A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

摘要翻译： 提供了一种制造具有改进的栅极特性的RF增强型FET（30）的方法。 该方法包括以下步骤：提供（131）具有形成在其上的半导体层（32-35）的堆叠的衬底（31），所述堆叠包括限定器件沟道的覆盖层（35）和中心层（33） 在所述盖层上形成（103）光致抗蚀剂图案（58），由此限定掩蔽区域和未掩蔽区域，并且以任何顺序，（a）在所述未掩蔽区域中产生（105）植入区域（36,37） ，和（b）从未掩蔽区域移除（107）盖层。 通过不重叠地形成注入区域和盖子区域，可以实现具有低电流泄漏的装置。

公开(公告)号：US5956578A

公开(公告)日：1999-09-21

申请号：US839226

申请日：1997-04-23

申请人： Charles E. Weitzel ,  Christine Thero ,  Mohit Bhatnagar

发明人： Charles E. Weitzel ,  Christine Thero ,  Mohit Bhatnagar

IPC分类号： H01L27/06 ,  H01L21/332

CPC分类号： H01L27/0605

摘要： A method of fabricating an integrated VFET and Schottky diode including forming a source region on the upper surface of a substrate so as to define a channel. First and second spaced apart gates are formed on opposing sides of the source region so as to abut the channel, thereby forming a channel structure. Schottky metal is positioned on the upper surface of the substrate proximate the channel structure to define a Schottky diode region and form a Schottky diode. A source contact is formed in communication with the source region and the Schottky metal, and a drain contact is formed on the lower surface of the substrate.

摘要翻译： 一种制造集成的VFET和肖特基二极管的方法，包括在衬底的上表面上形成源极区以形成沟道。 第一和第二间隔开的栅极形成在源极区域的相对侧上，以便邻接沟道，从而形成沟道结构。 肖特基金属位于靠近通道结构的衬底的上表面上以限定肖特基二极管区并形成肖特基二极管。 源极接触形成为与源极区域和肖特基金属连通，并且在衬底的下表面上形成漏极接触。

公开(公告)号：US5780878A

公开(公告)日：1998-07-14

申请号：US681684

申请日：1996-07-29

申请人： Mohit Bhatnagar ,  Charles E. Weitzel

发明人： Mohit Bhatnagar ,  Charles E. Weitzel

IPC分类号： H01L21/04 ,  H01L21/336 ,  H01L29/10 ,  H01L29/20 ,  H01L29/24 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7828 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

摘要： A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an accumulation region extending laterally adjacent the control terminal and communicating with the drift region and the source.

摘要翻译： 横向栅极，垂直漂移区晶体管，其包括位于衬底的一个表面上的漏极和其中位于衬底的另一表面上的埋入区的掺杂结构。 所述掩埋区域限定在所述掺杂结构中的漂移区域，所述漂移区域从所述衬底垂直延伸，并进一步限定与所述漂移区域相邻并且与所述掺杂结构的表面相邻的掺杂区域。 位于与掺杂区域连通的掺杂结构上的源极。 绝缘层，其位于所述掺杂结构上，金属栅极位于所述绝缘层上，以便限定横向延伸延伸到所述控制端并与所述漂移区和所述源连通的累积区。

公开(公告)号：US5677230A

公开(公告)日：1997-10-14

申请号：US566333

申请日：1995-12-01

申请人： Charles E. Weitzel ,  Edward L. Fisk ,  Sung P. Pack

发明人： Charles E. Weitzel ,  Edward L. Fisk ,  Sung P. Pack

IPC分类号： H01L21/3105 ,  H01L21/76 ,  H01L21/762 ,  H01L21/302 ,  H01L21/304 ,  H01L21/306

CPC分类号： H01L21/7605 ,  H01L21/31051 ,  H01L21/7602 ,  H01L21/76224 ,  Y10S438/906

摘要： A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

摘要翻译： 平面化宽度带隙半导体器件的方法，该宽带隙半导体器件从包括SiC，GaN和金刚石的组中选择，其具有通过深度为1至2微米和宽度为2至10微米的沟槽在其上限定的台面。 介电材料层沉积在覆盖并围绕台面的基板上，高度大约等于台面的高度，并且电介质材料从台面顶部和周围区域被蚀刻。 沉积玻璃上的层以填充周围区域并蚀刻以实现包括台面和电介质材料层的平面。

公开(公告)号：US5612232A

公开(公告)日：1997-03-18

申请号：US625605

申请日：1996-03-29

申请人： Christine Thero ,  Mohit Bhatnagar ,  Charles E. Weitzel

发明人： Christine Thero ,  Mohit Bhatnagar ,  Charles E. Weitzel

IPC分类号： H01L21/04 ,  H01L21/265 ,  H01L21/20 ,  H01L21/44

CPC分类号： H01L29/6606

摘要： A method of fabricating a semiconductor device including forming a Schottky contact on the surface of a substrate by patterning a layer of nickel to define a contact and annealing the nickel below approximately 600.degree. C. A trench is etched around the Schottky contact utilizing the Schottky contact as an etch mask and inert ions are implanted in the trench to form a damage region. The trench is passivated with a dielectric layer. An ohmic contact can be formed on the reverse side of the substrate prior to formation of the Schottky contact.

摘要翻译： 一种制造半导体器件的方法，包括通过对镍层进行图案化以形成接触并将镍退火到约600℃以下，在衬底的表面上形成肖特基接触。利用肖特基接触，在肖特基接触周围蚀刻沟槽 作为蚀刻掩模，并且将惰性离子注入到沟槽中以形成损伤区域。 沟槽用介电层钝化。 在形成肖特基接触之前，可以在衬底的背面形成欧姆接触。

公开(公告)号：US4969032A

公开(公告)日：1990-11-06

申请号：US220279

申请日：1988-07-18

申请人： Douglas G. Scheitlin ,  Charles E. Weitzel

发明人： Douglas G. Scheitlin ,  Charles E. Weitzel

IPC分类号： H01L27/06 ,  H01L29/808 ,  H01L29/92

CPC分类号： H01L27/0605 ,  H01L27/0688 ,  H01L28/40 ,  H01L29/808 ,  Y10S505/856

摘要： A monolithic microwave integrated circuit having multiple, vetically stacked components wherein at least three metal layers isolated from each other by layers of non-conducting material are formed on a semi-insulating substrate, generally comprised of gallium arsenide. Vertically stacked capacitors, inductors and various combinations thereof may be fabricated using the present invention. Further, the vetrically stacked components may be formed on active devices such as FETs and diodies.

摘要翻译： 一种单片微波集成电路，其具有多个卷积的元件，其中通过非导电材料层彼此隔离的至少三个金属层形成在通常由砷化镓组成的半绝缘基板上。 可以使用本发明制造垂直堆叠的电容器，电感器及其各种组合。 此外，可以在诸如FET和二极体之类的有源器件上形成该层叠的元件。

公开(公告)号：US07253455B2

公开(公告)日：2007-08-07

申请号：US11100095

申请日：2005-04-05

申请人： Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Philip H. Li ,  Monte G. Miller ,  Matthias Passlack ,  Marcus R. Ray ,  Charles E. Weitzel

发明人： Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Philip H. Li ,  Monte G. Miller ,  Matthias Passlack ,  Marcus R. Ray ,  Charles E. Weitzel

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L29/06

CPC分类号： H01L29/7785

摘要： In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1−xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1−xAs channel layer (512) is formed over the AlxGa1−xAs layer (506). An AlxGa1−xAs layer (518) is formed over the InxGa1−xAs channel layer (512), and the AlxGa1−xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1−xAs layer (518). A control electrode (526) is formed over the AlxGa1−xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

摘要翻译： 在一个实施例中，半导体器件（500）包括形成在衬底（502）上的缓冲层（504）。 在缓冲层（504）之上形成Al x Ga 1-x As层（506），并且在其中形成有第一掺杂区域（508）。 在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层（512） >作为层（506）。 在In 1 x 1 Ga 1-x N上形成Al x Ga 1-x As层（518） 作为沟道层（512）和Al x Ga 1-x As层（518）具有形成在其中的第二掺杂区域。 具有第一凹陷的GaAs层（520）形成在Al 1 Ga 1-x As层（518）上。 控制电极（526）形成在Al 1 Ga 1-x As As层（518）上。 在未掺杂的GaAs层（520）上和控制电极（526）的相对侧上形成掺杂GaAs层（524），并提供第一和第二电流电极。 当用于放大数字调制信号时，半导体器件（500）在宽的温度范围内保持线性操作。

公开(公告)号：US07229903B2

公开(公告)日：2007-06-12

申请号：US10925855

申请日：2004-08-25

申请人： Hsin-Hua P. Li ,  Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Charles E. Weitzel

发明人： Hsin-Hua P. Li ,  Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Charles E. Weitzel

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7785 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

摘要翻译： 半导体结构包括第一半导体层，第一半导体层上的第二半导体层，第二半导体层上的第三半导体层以及第三半导体层上的第四半导体层。 第一导电部分耦合到第一半导体层，并且在第一半导体层上形成第二导电部分。