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公开(公告)号：US20140209892A1
公开(公告)日：2014-07-31
申请号：US13997392
申请日：2012-04-12
CPC分类号： H01L43/10 , G11C5/025 , G11C5/063 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C13/003 , G11C2213/15 , G11C2213/71 , H01L43/12
摘要： Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).
摘要翻译： 公开了能够实现低电压嵌入式存储器应用的技术，材料和电路。 在一个示例性实施例中，嵌入式存储器配置有具有存储器元件和串行连接在字线和位线的交叉点之间的选择器元件的位单元。 选择器元件可以例如用任何数量的表现出S形电流 - 电压（IV）曲线的结晶材料来实现，或者否则在超过阈值标准之后能使得在选择器电压中的回跳。 选择器的快速恢复被有效地用于在给定的最大电源电压下适应选择器的导通状态电压，其中在没有快速恢复的情况下，导通状态电压将超过该最大供电电压。 在一些示例性实施例中，最大供电电压小于1伏特（例如，0.9伏或更小）。
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公开(公告)号：US09543507B2
公开(公告)日：2017-01-10
申请号：US13997392
申请日：2012-04-12
CPC分类号： H01L43/10 , G11C5/025 , G11C5/063 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C13/003 , G11C2213/15 , G11C2213/71 , H01L43/12
摘要： Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).
摘要翻译： 公开了能够实现低电压嵌入式存储器应用的技术，材料和电路。 在一个示例性实施例中，嵌入式存储器配置有具有存储器元件和串行连接在字线和位线的交叉点之间的选择器元件的位单元。 选择器元件可以例如用任何数量的表现出S形电流 - 电压（IV）曲线的结晶材料来实现，或者否则在超过阈值标准之后能使得在选择器电压中的回跳。 选择器的快速恢复被有效地用于在给定的最大电源电压下适应选择器的导通状态电压，其中在没有快速恢复的情况下，导通状态电压将超过该最大供电电压。 在一些示例性实施例中，最大供电电压小于1伏特（例如，0.9伏或更小）。
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公开(公告)号：US20140291663A1
公开(公告)日：2014-10-02
申请号：US13996603
申请日：2013-03-28
申请人： Charles Kuo , Kaan Oguz , Brian Doyle , Elijah Ilya Karpov , Roksana Golizadeh Mojarad , David Kencke , Robert Chau
发明人： Charles Kuo , Kaan Oguz , Brian Doyle , Elijah Ilya Karpov , Roksana Golizadeh Mojarad , David Kencke , Robert Chau
CPC分类号： H01L43/10 , G11C11/161 , H01F10/3286 , H01F10/329 , H01L43/065 , H01L43/08 , H01L43/12 , H01L43/14
摘要： An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.
摘要翻译： 实施例包括在自由层和固定层之间包括自由磁性层，固定磁性层和隧道势垒的磁性隧道结（MTJ）; 所述隧道势垒直接接触所述自由层的第一侧; 和直接接触自由层的第二面的氧化物层; 其中所述隧道势垒包括氧化物并且具有第一电阻区域（RA）产物，并且所述氧化物层具有低于所述第一RA产物的第二RA产物。 MTJ可以包括在垂直旋转扭矩传递存储器中。 隧道势垒和氧化物层形成具有高稳定性的存储器，RA产物实质上高于具有仅具有单一氧化物层的MTJ的较少表存储器。 本文描述了其它实施例。
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公开(公告)号：US20080029752A1
公开(公告)日：2008-02-07
申请号：US11771601
申请日：2007-06-29
申请人： Ilya Karpov , Charles Kuo , Yudong Kim , Greg Atwood
发明人： Ilya Karpov , Charles Kuo , Yudong Kim , Greg Atwood
CPC分类号： H01L45/04 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1683
摘要： Both a chalcogenide select device (24, 120) and a chalcogenide memory element (40, 130) are formed within vias within dielectrics (18, 22). As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material (30) is formed within the same via (31) with the memory element (40, 130). In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer (28); in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide (40) used to form a memory element (130) and the lance material (30) is achieved by providing a pin hole opening in a dielectric (34), which separates the chalcogenide and the lance material.
摘要翻译： 在电介质（18,22）内的通孔内形成硫族化物选择装置（24,120）和硫族化物存储元件（40,130）。 结果，硫属化物被有效地捕获在通孔内，并且不需要胶或粘合层。 此外，避免了分层问题。 在与存储元件（40,130）相同的通孔（31）内形成喷枪材料（30）。 在一个实施例中，由于存在侧壁间隔件（28），喷枪材料制成更薄。 在另一个实施例中，没有使用侧壁间隔物。 用于形成存储元件（130）的硫族化物（40）与喷枪材料（30）之间的相对小的接触面积是通过在电介质（34）中设置一个针孔开口来实现的，该电介质（34）将硫族化物和喷枪 材料。
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公开(公告)号：US20060257787A1
公开(公告)日：2006-11-16
申请号：US11127482
申请日：2005-05-12
申请人： Charles Kuo , Ilya Karpov
发明人： Charles Kuo , Ilya Karpov
IPC分类号： G11B7/24
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/1683 , Y10S438/90
摘要： A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments.
摘要翻译： 可以形成适于多级编程的相变存储器。 相变材料可以形成有不超过下面的加热器的横向范围的横向范围。 结果，减少了在复位状态下绕过非晶相变材料的电流的可能性，从而减少了防止这种情况所必需的编程电流。 此外，在一些实施例中可以形成更可控的多电平相变存储器。
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6.发明授权Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element 有权用于制造铜兼容的硫族化物相变存储元件和相应的相变存储元件的工艺公开(公告)号：US08222627B2
公开(公告)日：2012-07-17
申请号：US12174462
申请日：2008-07-16
申请人： Charles Kuo , Yudong Kim
发明人： Charles Kuo , Yudong Kim
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/1266 , H01L45/141 , H01L45/144 , H01L45/1683
摘要： A copper-diffusion plug 21 is provided within a pore in dielectric layer over a copper signal line. By positioning the plug below a chalcogenide region, the plug is effective to block copper diffusion upwardly into the pore and into the chalcogenide region and thus to avoid adversely affecting the electrical characteristics of the chalcogenide region.
摘要翻译： 铜扩散塞21设置在铜信号线上的电介质层的孔内。 通过将塞子定位在硫族化物区域下方，塞子有效地阻止铜扩散到孔中并进入硫族化物区域，从而避免不利地影响硫族化物区域的电特性。
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公开(公告)号：US07847333B2
公开(公告)日：2010-12-07
申请号：US12055216
申请日：2008-03-25
申请人： Charles Kuo , Yudong Kim
发明人： Charles Kuo , Yudong Kim
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/6653 , H01L29/66553
摘要： Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is formed on the top and sidewalls of the first gate fin and portions of the first gate base. A second gate is formed on the second insulating layer. Source and drain regions are formed in the substrate at opposite sides of the first gate base. In one embodiment, the first gate fin includes an undoped polysilicon and the first gate base includes an n-type polysilicon. In another embodiment, the first gate fin includes an undoped amorphous silicon and the first gate base includes an n-type amorphous silicon.
摘要翻译： 描述半导体存储器件及其制造方法。 在基板上的第一绝缘层上形成第一栅极基底。 第一栅极鳍形成在第一栅极基底上。 第一个门鳍具有顶部和侧壁。 接下来，在第一栅极鳍的顶部和侧壁以及第一栅极基底的一部分上形成第二绝缘层。 第二栅极形成在第二绝缘层上。 源极和漏极区域形成在第一栅极基极的相对侧的衬底中。 在一个实施例中，第一栅极鳍包括未掺杂多晶硅，第一栅极基底包括n型多晶硅。 在另一个实施例中，第一栅极鳍包括未掺杂的非晶硅，第一栅极基底包括n型非晶硅。
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公开(公告)号：US20070259479A1
公开(公告)日：2007-11-08
申请号：US11827223
申请日：2007-07-11
申请人： Charles Kuo , Ilya Karpov , Yudong Kim , Greg Atwood
发明人： Charles Kuo , Ilya Karpov , Yudong Kim , Greg Atwood
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1691 , Y10S438/947
摘要： A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then be removed and the remaining portions of the mask may be used to define a dimension of said phase change material. Another dimension of the phase change material may be defined using an upper electrode extending over said phase change material as a mask to etch the phase change material.
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9.发明申请Programming a normally single phase chalcogenide material for use as a memory or FPLA 有权编程正常的单相硫属化物材料，用作记忆体或FPLA公开(公告)号：US20070247899A1
公开(公告)日：2007-10-25
申请号：US11407573
申请日：2006-04-20
申请人： George Gordon , Ward Parkinson , John Peters , Tyler Lowrey , Stanford Ovshinsky , Guy Wicker , Ilya Karpov , Charles Kuo
发明人： George Gordon , Ward Parkinson , John Peters , Tyler Lowrey , Stanford Ovshinsky , Guy Wicker , Ilya Karpov , Charles Kuo
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译： 可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。 可以通过改变材料的阈值电压来编程不同的状态。 可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。 可以使用两种不同状态的阈值电压之间的参考电平进行读取。 通常不需要单独的访问设备。
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公开(公告)号：US20070037487A1
公开(公告)日：2007-02-15
申请号：US11492409
申请日：2006-07-25
申请人： Charles Kuo , Jennifer O'Sullivan
发明人： Charles Kuo , Jennifer O'Sullivan
CPC分类号： B24B37/205
摘要： The present invention provides a chemical mechanical polishing pad comprising a window formed in the polishing pad, the window having a void provided on a side thereof. The invention further provides a pressure relief channel provided in the polishing pad from the void to a periphery of the polishing pad. In addition, a membrane is provided in the channel to prevent contamination of the void.
摘要翻译： 本发明提供了一种化学机械抛光垫，其包括在抛光垫中形成的窗口，该窗口在其一侧具有空隙。 本发明还提供一种设置在抛光垫中的压力释放通道，该压力释放通道从抛光垫的空隙到周边。 此外，在通道中设置膜以防止空隙的污染。
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