公开(公告)号：US20080217775A1

公开(公告)日：2008-09-11

申请号：US11714770

申请日：2007-03-07

申请人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

发明人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76849 ,  H01L27/10855 ,  H01L27/10888

摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.

摘要翻译： 形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层 和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

公开(公告)号：US08643074B2

公开(公告)日：2014-02-04

申请号：US13462427

申请日：2012-05-02

申请人： Chih-Yang Pai ,  Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chung-Yen Chou

发明人： Chih-Yang Pai ,  Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chung-Yen Chou

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶部电极，底部电极和介于 所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

公开(公告)号：US08617949B2

公开(公告)日：2013-12-31

申请号：US13267424

申请日：2011-10-06

申请人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.

摘要翻译： 片上系统装置包括第一区域中的第一电容器，第二区域中的第二电容器，并且还可以包括第三区域中的第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容器绝缘体可以具有不同数量的亚层，形成不同的材料或厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域等。

公开(公告)号：US20130020678A1

公开(公告)日：2013-01-24

申请号：US13188343

申请日：2011-07-21

申请人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L27/0207 ,  H01L28/40

摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.

摘要翻译： 公开了具有无取向去耦电容器的半导体器件及其制造方法。 在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。 至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

公开(公告)号：US06794254B1

公开(公告)日：2004-09-21

申请号：US10438646

申请日：2003-05-15

申请人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis J. Sinitsky

发明人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis J. Sinitsky

IPC分类号： H01L21336

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.

摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

公开(公告)号：US06638813B1

公开(公告)日：2003-10-28

申请号：US10059825

申请日：2002-01-29

申请人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

发明人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11

摘要： A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.

摘要翻译： 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

公开(公告)号：US06420226B1

公开(公告)日：2002-07-16

申请号：US10020753

申请日：2001-12-12

申请人： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

发明人： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/11 ,  H01L28/91 ,  H01L29/66181

摘要： A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

摘要翻译： 已经开发了用于单晶体管，RAM单元中的埋层叠层电容器结构的制造工艺。 该方法特征在于通过选择性干法蚀刻工艺形成形成在氧化硅填充的浅沟槽形状的顶部的自对准的环形存储节点开口。 选择性干蚀刻方法与随后的选择性湿法蚀刻程序结合，在环形存储节点开口和相邻的半导体顶表面的接合处产生半导体衬底的裸露部分，允许在该区域中产生重掺杂区域。 当在环形存储节点结构中形成存储节点结构时，以及在重掺杂区域上覆盖时，重掺杂区域的存在将节点与衬底电阻降低。

公开(公告)号：US06403416B1

公开(公告)日：2002-06-11

申请号：US09226279

申请日：1999-01-07

申请人： Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

发明人： Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

IPC分类号： H01L218242

CPC分类号： H01L28/91

摘要： A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.

摘要翻译： 描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。 第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。 沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。 沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。 使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。 沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。 在热磷酸中除去第一和第二Si 3 N 4层。 电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。

公开(公告)号：US5968278A

公开(公告)日：1999-10-19

申请号：US206744

申请日：1998-12-07

申请人： Bao-Ru Young ,  Chia-Shiung Tsai ,  Wen-Chuan Chiang

发明人： Bao-Ru Young ,  Chia-Shiung Tsai ,  Wen-Chuan Chiang

IPC分类号： H01L21/311 ,  H01L21/768 ,  B08B6/00

CPC分类号： H01L21/76816 ,  H01L21/31138

摘要： An improved etching procedure that uses three processing steps to vastly improve HAR opening profile and improved under-layer selectivity. A new three sequence etching process is provided during which a new three-gas plasma etch is to be used. This new etching sequence is preceded by a new main etch that uses three gasses and followed by a new over-etch procedure that uses the same three gasses and etching conditions as the new main etch.

摘要翻译： 改进的蚀刻步骤使用三个加工步骤大大改善HAR开口轮廓和改进的底层选择性。 提供了一种新的三序蚀刻工艺，其中将使用新的三气等离子体蚀刻。 这个新的蚀刻序列之前是一个新的主要蚀刻，使用三个气体，然后采用与新的主蚀刻相同的三个气体和蚀刻条件的新的过蚀刻程序。

公开(公告)号：US20140042590A1

公开(公告)日：2014-02-13

申请号：US13571441

申请日：2012-08-10

申请人： Kuo-Ji Chen ,  Wen-Chuan Chiang ,  Huey-Chi Chu ,  Ming-Hsiang Song ,  Chen-Jong Wang

发明人： Kuo-Ji Chen ,  Wen-Chuan Chiang ,  Huey-Chi Chu ,  Ming-Hsiang Song ,  Chen-Jong Wang

IPC分类号： H01L29/92

CPC分类号： H01L28/60 ,  H01L28/75 ,  H01L29/92

摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.

摘要翻译： 公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。 当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。