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公开(公告)号：US20120038044A1
公开(公告)日：2012-02-16
申请号：US12959148
申请日：2010-12-02
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/82 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/12105 , H01L2224/24225 , H01L2224/25171 , H01L2224/32155 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/3511
摘要： A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.
摘要翻译： CSP包括：具有带导电焊盘的第一布线层的硬板; 布置在所述导电垫的至少一部分上的多个导电元件; 电子元件具有相反的有源和无效表面，并且经由非活性表面安装在硬板上; 设置在所述硬板上用于封装所述导电元件和电子部件的封装层，所述电子部件的所述有源表面和所述导电元件的表面通过所述封装层露出; 设置在所述封装层上的第一电介质层和第三布线层，所述第三布线层电连接到所述导电元件和所述电子部件，并且还通过所述导电元件与所述第一布线层电连接，从而获得堆叠连接结构 不需要PTH和使用硬板作为主要结构，以避免翘曲。
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2.发明授权Chip scale package with electronic component received in encapsulant, and fabrication method thereof 有权具有接收在密封剂中的电子部件的芯片级封装及其制造方法公开(公告)号：US09040361B2
公开(公告)日：2015-05-26
申请号：US12959148
申请日：2010-12-02
CPC分类号： H01L24/82 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/12105 , H01L2224/24225 , H01L2224/25171 , H01L2224/32155 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/3511
摘要： A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.
摘要翻译： CSP包括：具有带导电焊盘的第一布线层的硬板; 布置在所述导电垫的至少一部分上的多个导电元件; 电子元件具有相反的有源和无效表面，并且经由非活性表面安装在硬板上; 设置在所述硬板上用于封装所述导电元件和电子部件的封装层，所述电子部件的所述有源表面和所述导电元件的表面通过所述封装层露出; 设置在所述封装层上的第一电介质层和第三布线层，所述第三布线层电连接到所述导电元件和所述电子部件，并且还通过所述导电元件与所述第一布线层电连接，从而获得堆叠连接结构 不需要PTH和使用硬板作为主要结构，以避免翘曲。
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公开(公告)号：US20120313243A1
公开(公告)日：2012-12-13
申请号：US13221323
申请日：2011-08-30
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/3128 , H01L23/3114 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2924/18162
摘要： A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer.
摘要翻译： 芯片级封装包括封装层，嵌入封装层中的芯片，并且具有从封装层露出的有源表面，形成在封装层和芯片上的缓冲电介质层，形成在封装层上的积聚介电层 缓冲电介质层和形成在积聚电介质层上的电路层，并且具有穿透积聚介电层并且与缓冲电介质层的开口连通并且电连接到芯片的导电盲孔，其中构建 介电层和缓冲电介质层由不同的材料制成。 因此，缓冲电介质层和封装层之间不会发生分层，因为缓冲电介质层牢固地结合到封装层，并且缓冲电介质层均匀地分布在封装层上。
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公开(公告)号：US08420430B2
公开(公告)日：2013-04-16
申请号：US12769087
申请日：2010-04-28
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
摘要翻译： 提供具有至少MEMS元件的封装结构的制造方法，包括：制备具有电连接焊盘和所述至少MEMS元件的晶片; 设置用于覆盖所述至少一个MEMS元件的盖，所述盖具有在其上形成的金属层; 电连接焊盘和金属层与接合线; 形成用于覆盖盖子，接合线，电连接垫和金属层的密封剂; 去除所述密封剂的部分以将所述接合线分别分离成第一和第二子接合线，其中所述第一和第二次接合线的顶端被暴露，所述第一子接合线电连接到所述电连接焊盘，以及 所述第二子接合线电连接到所述金属层; 在所述密封剂上形成用于电连接到所述第一子接合线的金属迹线; 在金属痕迹上形成凸块; 并执行单独处理。
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公开(公告)号：US20110177643A1
公开(公告)日：2011-07-21
申请号：US12769087
申请日：2010-04-28
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
摘要翻译： 提供具有至少MEMS元件的封装结构的制造方法，包括：制备具有电连接焊盘和所述至少MEMS元件的晶片; 设置用于覆盖所述至少一个MEMS元件的盖，所述盖具有在其上形成的金属层; 电连接焊盘和金属层与接合线; 形成用于覆盖盖子，接合线，电连接垫和金属层的密封剂; 去除所述密封剂的部分以将所述接合线分别分离成第一和第二子接合线，其中所述第一和第二次接合线的顶端被暴露，所述第一子接合线电连接到所述电连接焊盘，以及 所述第二子接合线电连接到所述金属层; 在所述密封剂上形成用于电连接到所述第一子接合线的金属迹线; 在金属痕迹上形成凸块; 并执行单独处理。
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公开(公告)号：US20110175179A1
公开(公告)日：2011-07-21
申请号：US12769993
申请日：2010-04-29
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.
摘要翻译： 提供具有至少MEMS元件的封装结构，其包括具有电连接焊盘和MEMS元件的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有设置在其上的金属层的盖; 电连接到电连接焊盘的第一子接合线; 电连接到金属层的第二子接合线; 设置在所述芯片上的密封剂，其中所述第一和第二子接合线的顶端从所述密封剂露出; 以及设置在密封剂上并电连接到第一子接合线的金属迹线。 封装结构有利地具有减小的尺寸，相对低的成本，不同的凸起位置和增强的EMI屏蔽效果。
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公开(公告)号：US08866236B2
公开(公告)日：2014-10-21
申请号：US12769993
申请日：2010-04-29
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.
摘要翻译： 提供具有至少MEMS元件的封装结构，其包括具有电连接焊盘和MEMS元件的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有设置在其上的金属层的盖; 电连接到电连接焊盘的第一子接合线; 电连接到金属层的第二子接合线; 设置在所述芯片上的密封剂，其中所述第一和第二子接合线的顶端从所述密封剂露出; 以及设置在密封剂上并电连接到第一子接合线的金属迹线。 封装结构有利地具有减小的尺寸，相对低的成本，不同的凸起位置和增强的EMI屏蔽效果。
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公开(公告)号：US08334174B2
公开(公告)日：2012-12-18
申请号：US12862473
申请日：2010-08-24
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L21/561 , H01L23/49827 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L24/19 , H01L24/20 , H01L25/03 , H01L25/0655 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/211 , H01L2224/221 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/3511 , H01L2224/05599 , H01L2224/05099
摘要： A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.
摘要翻译： 芯片级封装的制造方法包括：在载板上设置芯片并将芯片嵌入具有硬层和软层的复合板中; 并移除载体板以进行再分布层（RDL）处理，从而解决了将由芯片直接附着在粘合膜上的常规问题，例如由热引起的薄膜软化，密封剂溢出，芯片偏移和污染， 所有这些都可能导致在随后的RDL过程中布线层和芯片电极垫之间的电连接不良，甚至结果导致废物。
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公开(公告)号：US20120086117A1
公开(公告)日：2012-04-12
申请号：US12965215
申请日：2010-12-10
CPC分类号： H01L23/5389 , H01L23/4334 , H01L23/49816 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/2518 , H01L2224/32245 , H01L2224/73267 , H01L2225/1035 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511
摘要： A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.
摘要翻译： 嵌入芯片的封装以及制造嵌入式芯片封装的方法。 嵌入式芯片的封装包括具有与第一表面相对的第一表面和第二表面的电介质层; 形成在电介质层中并从电介质层的第二表面露出的多个导电柱; 嵌入在介电层中的芯片; 形成在电介质层的第一表面上的电路层; 形成在所述电介质层中的多个导电盲孔，允许所述电路层经由所述导电盲孔通向芯片和每个导电柱电连接; 以及形成在电介质层和电路层的第一表面上的第一焊料掩模层，从而根据需要使用导电柱来与其他电子器件外部连接以形成堆叠结构。 因此，可以有效地简化制造过程。
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公开(公告)号：US20120018870A1
公开(公告)日：2012-01-26
申请号：US12862473
申请日：2010-08-24
CPC分类号： H01L21/568 , H01L21/561 , H01L23/49827 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L24/19 , H01L24/20 , H01L25/03 , H01L25/0655 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/211 , H01L2224/221 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/3511 , H01L2224/05599 , H01L2224/05099
摘要： A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.
摘要翻译： 芯片级封装的制造方法包括：在载板上设置芯片并将芯片嵌入具有硬层和软层的复合板中; 并移除载体板以进行再分布层（RDL）处理，从而解决了将由芯片直接附着在粘合膜上的常规问题，例如由热引起的薄膜软化，密封剂溢出，芯片偏移和污染， 所有这些都可能导致在随后的RDL过程中布线层和芯片电极垫之间的电连接不良，甚至结果导致废物。
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