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    Method for detecting the under-fill void in flip chip BGA
    1.
    发明授权
    Method for detecting the under-fill void in flip chip BGA 有权
    用于检测倒装芯片BGA中欠补充空隙的方法

    公开(公告)号：US08518722B2

    公开(公告)日：2013-08-27

    申请号：US13064161

    申请日：2011-03-09

    申请人： Chien-Wen Chen ,  Chia-Jen Kao ,  Jui-Cheng Chuang

    发明人： Chien-Wen Chen ,  Chia-Jen Kao ,  Jui-Cheng Chuang

    IPC分类号： H01L21/66

    CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L22/12 ,  H01L23/055 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

    摘要： A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

    摘要翻译： 提供了一种用于检测倒装芯片球栅阵列封装结构的欠补充空隙的方法，其包括在其中提供具有互连结构的衬底和多个中介层; 提供具有活性表面和背面的芯片，以及在芯片的有源表面上的多个第一连接元件; 将所述芯片的有源表面安装并电连接在所述基板上; 执行至少一次IR回流以将所述多个第一连接元件固定在所述基板上; 填充封装材料以覆盖所述芯片的有效表面和所述多个第一连接元件; 执行检测处理以检测在所述芯片的有效表面和所述多个第一元件之间不形成所述空隙; 以及在所述基板的背面上形成多个第二连接元件以获得倒装芯片球栅阵列封装结构。

    Method for detecting the under-fill void in flip chip BGA
    2.
    发明申请
    Method for detecting the under-fill void in flip chip BGA 有权
    用于检测倒装芯片BGA中欠补充空隙的方法

    公开(公告)号：US20120052603A1

    公开(公告)日：2012-03-01

    申请号：US13064161

    申请日：2011-03-09

    申请人： Chien-Wen Chen ,  Chia-Jen Kao ,  Jui-Cheng Chuang

    发明人： Chien-Wen Chen ,  Chia-Jen Kao ,  Jui-Cheng Chuang

    IPC分类号： H01L21/66

    CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L22/12 ,  H01L23/055 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

    摘要： A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

    摘要翻译： 提供了一种用于检测倒装芯片球栅阵列封装结构的欠补充空隙的方法，其包括在其中提供具有互连结构的衬底和多个中介层; 提供具有活性表面和背面的芯片，以及在芯片的有源表面上的多个第一连接元件; 将所述芯片的有源表面安装并电连接在所述基板上; 执行至少一次IR回流以将所述多个第一连接元件固定在所述基板上; 填充封装材料以覆盖所述芯片的有效表面和所述多个第一连接元件; 执行检测处理以检测在所述芯片的有效表面和所述多个第一元件之间不形成所述空隙; 以及在所述基板的背面上形成多个第二连接元件以获得倒装芯片球栅阵列封装结构。

    WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD
    5.
    发明申请
    WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD 审中-公开
    水平可靠性增强系统及相关方法

    公开(公告)号：US20080270056A1

    公开(公告)日：2008-10-30

    申请号：US11740916

    申请日：2007-04-26

    申请人： Yun-Chi Yang ,  Cheng-Li Lin ,  Chia-Jen Kao ,  Ju-Ping Chen ,  Kuan-Cheng Su

    发明人： Yun-Chi Yang ,  Cheng-Li Lin ,  Chia-Jen Kao ,  Ju-Ping Chen ,  Kuan-Cheng Su

    IPC分类号： H01L21/66 ,  G01N37/00

    CPC分类号： H01L22/20

    摘要： A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.

    摘要翻译： 屈服增强系统具有制造线，其具有用于制造晶片的半导体制造装置，耦合到制造线的检查和测量监测系统，用于确定对应于半导体制造装置的工艺数据，以及耦合到制造线的后处理测试线 用于进行在线晶圆级测试。 后处理测试线包括晶片接收测试仪，耦合到晶片接收测试仪的屈服监测器，以及耦合到晶片接收测试仪的晶片级可靠性测试器，用于估计晶片上的器件的寿命。

    Method for monitoring oxide quality
    6.
    发明授权
    Method for monitoring oxide quality 有权
    监测氧化物质量的方法

    公开(公告)号：US06894517B2

    公开(公告)日：2005-05-17

    申请号：US10065432

    申请日：2002-10-17

    申请人： Ting-Kuo Kang ,  Yi-Fan Chen ,  Chia-Jen Kao

    发明人： Ting-Kuo Kang ,  Yi-Fan Chen ,  Chia-Jen Kao

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C29/00 ,  G01R31/02

    CPC分类号： G11C29/006 ,  G01R31/2648 ,  G01R31/2831

    摘要： The present invention utilizes to wafer acceptance testing equipment to fast monitor the quality of a tunnel oxide layer. First, a control gate and a floating gate in a memory cell are electrically connected. Then a plurality of swing time-dependent DC ramping voltages are applied and each corresponding gate leakage current is measured to calculate each corresponding β value. Finally a ratio of each β value is calculated and a β-gate voltage curve is plotted to actually simulate the device failure.

    摘要翻译： 本发明利用晶圆验收测试设备来快速监测隧道氧化层的质量。 首先，存储单元中的控制栅极和浮置栅极电连接。 然后施加多个摆动时间相关的DC斜坡电压，并且测量每个对应的栅极泄漏电流以计算每个对应的β值。 最后，计算每个β值的比率，并绘制一个β栅极电压曲线，以实际模拟器件故障。

    Electronic test system and associated method
    7.
    发明授权
    Electronic test system and associated method 有权
    电子测试系统及相关方法

    公开(公告)号：US08816708B2

    公开(公告)日：2014-08-26

    申请号：US13547094

    申请日：2012-07-12

    申请人： Shin-Cheng Chu ,  Ching-Tsung Chen ,  Teng-Hui Lee ,  Chia-Jen Kao

    发明人： Shin-Cheng Chu ,  Ching-Tsung Chen ,  Teng-Hui Lee ,  Chia-Jen Kao

    IPC分类号： G01R31/00 ,  G01R1/00 ,  G01R3/00 ,  G01R5/00 ,  G01R7/00 ,  G01R9/00 ,  G01R11/00 ,  G01R13/00 ,  G01R17/00 ,  G01R19/00 ,  G01R35/00

    CPC分类号： G01R1/00 ,  G01R3/00 ,  G01R5/00 ,  G01R7/00 ,  G01R9/00 ,  G01R11/00 ,  G01R13/00 ,  G01R17/00 ,  G01R19/00 ,  G01R31/002 ,  G01R31/129 ,  G01R35/00

    摘要： Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

    摘要翻译： 电子测试系统和相关方法，包括分别耦合到被测芯片的两个引脚的第一和第二连接端子，耦合到信号发生器的信号源端子，耦合到测试器的第一和第二测量端子，第五 开关，第七开关和开关电路，其具有耦合到信号源端子的第一和第四前端，具有耦合到第一和第二连接端子的第一和第四后端子，并且控制第一前端子 和第一后端子，以及第四前端子和第四后端子之间的导通。 第五开关耦合在第四后端子和第一测量端子之间，第七开关耦合在第一连接端子和第二测量端子之间。

    METHOD FOR MONITORING QUALITY OF AN INSULATION LAYER
    8.
    发明申请
    METHOD FOR MONITORING QUALITY OF AN INSULATION LAYER 有权
    用于监测绝缘层质量的方法

    公开(公告)号：US20050040840A1

    公开(公告)日：2005-02-24

    申请号：US10710724

    申请日：2004-07-30

    申请人： Ting-Kuo Kang ,  Yi-Fan Chen ,  Chia-Jen Kao

    发明人： Ting-Kuo Kang ,  Yi-Fan Chen ,  Chia-Jen Kao

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C29/00 ,  H01L21/8222

    CPC分类号： G01R31/2831 ,  G01R31/2648 ,  G11C29/006 ,  H01L22/14

    摘要： The present invention utilizes wafer acceptance testing equipment to fast monitor the quality of an insulation layer. A plurality of swing time-dependent DC ramping voltages are applied to one of the electrode plates in a capacitor and each corresponding leakage current is measured to calculate each corresponding β value. Then, a ratio of each β value is calculated and a β− voltage curve is plotted to actually simulate the device failure.

    摘要翻译： 本发明利用晶片验收测试设备来快速监测绝缘层的质量。 将多个摆动时间相关的DC斜坡电压施加到电容器中的一个电极板，并且测量每个相应的泄漏电流以计算每个对应的β值。 然后，计算每个β值的比率，并绘制一个电压 - 曲线，以实际模拟器件故障。

    ELECTRONIC TEST SYSTEM AND ASSOCIATED METHOD
    9.
    发明申请
    ELECTRONIC TEST SYSTEM AND ASSOCIATED METHOD 有权
    电子测试系统及相关方法

    公开(公告)号：US20130113508A1

    公开(公告)日：2013-05-09

    申请号：US13547094

    申请日：2012-07-12

    申请人： Shin-Cheng Chu ,  Ching-Tsung Chen ,  Teng-Hui Lee ,  Chia-Jen Kao

    发明人： Shin-Cheng Chu ,  Ching-Tsung Chen ,  Teng-Hui Lee ,  Chia-Jen Kao

    IPC分类号： G01R31/00

    CPC分类号： G01R1/00 ,  G01R3/00 ,  G01R5/00 ,  G01R7/00 ,  G01R9/00 ,  G01R11/00 ,  G01R13/00 ,  G01R17/00 ,  G01R19/00 ,  G01R31/002 ,  G01R31/129 ,  G01R35/00

    摘要： Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

    摘要翻译： 电子测试系统和相关方法，包括分别耦合到被测芯片的两个引脚的第一和第二连接端子，耦合到信号发生器的信号源端子，耦合到测试器的第一和第二测量端子，第五 开关，第七开关和开关电路，其具有耦合到信号源端子的第一和第四前端，具有耦合到第一和第二连接端子的第一和第四后端子，并且控制第一前端子 和第一后端子，以及第四前端子和第四后端子之间的导通。 第五开关耦合在第四后端子和第一测量端子之间，第七开关耦合在第一连接端子和第二测量端子之间。

    Method for monitoring quality of an insulation layer
    10.
    发明授权
    Method for monitoring quality of an insulation layer 有权
    监测绝缘层质量的方法

    公开(公告)号：US07019545B2

    公开(公告)日：2006-03-28

    申请号：US10710724

    申请日：2004-07-30

    申请人： Ting-Kuo Kang ,  Yi-Fan Chen ,  Chia-Jen Kao

    发明人： Ting-Kuo Kang ,  Yi-Fan Chen ,  Chia-Jen Kao

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2831 ,  G01R31/2648 ,  G11C29/006 ,  H01L22/14

    摘要： The present invention utilizes wafer acceptance testing equipment to fast monitor the quality of an insulation layer. A plurality of swing time-dependent DC ramping voltages are applied to one of the electrode plates in a capacitor and each corresponding leakage current is measured to calculate each corresponding β value. Then, a ratio of each β value is calculated and a β-voltage curve is plotted to actually simulate the device failure.

    摘要翻译： 本发明利用晶片验收测试设备来快速监测绝缘层的质量。 将多个摆动时间相关的DC斜坡电压施加到电容器中的一个电极板，并且测量每个相应的泄漏电流以计算每个对应的β值。 然后，计算每个β值的比率，并绘制β电压曲线以实际模拟器件故障。