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38 条记录 (耗时 0.022 秒)

    Delay-locked loop
    1.
    发明授权
    Delay-locked loop 有权
    延迟锁定环路

    公开(公告)号：US08368445B2

    公开(公告)日：2013-02-05

    申请号：US13174798

    申请日：2011-07-01

    申请人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    发明人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/1075

    摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

    摘要翻译： 提供接收参考时钟信号并输出​​输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。 相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。 延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。 环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

    DELAY-LOCKED LOOP
    2.
    发明申请
    DELAY-LOCKED LOOP 有权
    延迟锁定

    公开(公告)号：US20130002320A1

    公开(公告)日：2013-01-03

    申请号：US13174798

    申请日：2011-07-01

    申请人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    发明人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/1075

    摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

    摘要翻译： 提供接收参考时钟信号并输出​​输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。 相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。 延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。 环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

    Fiber container and associated optical communication device
    7.
    发明授权
    Fiber container and associated optical communication device 失效
    光纤容器及相关光通讯装置

    公开(公告)号：US06873778B2

    公开(公告)日：2005-03-29

    申请号：US10291836

    申请日：2002-11-12

    申请人： Tsung-Yueh Tsai ,  Chin-Hsiang Wang ,  Yu-Ting Lee ,  Chih-Hsien Lin

    发明人： Tsung-Yueh Tsai ,  Chin-Hsiang Wang ,  Yu-Ting Lee ,  Chih-Hsien Lin

    IPC分类号： B65H18/08 ,  G02B6/00 ,  H01S3/067

    CPC分类号： H01S3/06704

    摘要： A fiber container receiving optical fibers has a body, a space defined in the body, a reel disposed inside the body, wherein a groove is defined around the periphery of the reel. The optical fibers are twisted around the reel and received in the groove. Furthermore, the fiber container is able to apply to the active/passive optical communication device, such as an erbium doped fiber amplifier (EDFA) or a dense wavelength division multiplexer (DWDM).

    摘要翻译： 容纳光纤的纤维容器具有主体，在主体中限定的空间，设置在主体内部的卷轴，其中围绕卷轴的周边限定有凹槽。 光纤绕卷轴扭转并被接收在槽中。 此外，光纤容器能够应用于有源/无源光通信设备，例如掺铒光纤放大器（EDFA）或密集波分复用器（DWDM）。

    Method of forming resistors
    8.
    发明授权
    Method of forming resistors 有权
    形成电阻的方法

    公开(公告)号：US06732422B1

    公开(公告)日：2004-05-11

    申请号：US10037811

    申请日：2002-01-04

    申请人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

    发明人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

    IPC分类号： H01C1700

    CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/0656 ,  H01C17/075 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49098

    摘要： A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.

    摘要翻译： 描述形成电阻器的方法，其实现了电阻器稳定性和电阻的电压系数的改善。 电阻器由诸如掺杂硅或多晶硅的导电材料形成。 电阻器具有矩形的第一，第二，第三，第四和第五电阻元件。 在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。 然后将暴露的第四和第五电阻器元件中的导电材料改变为硅化物以在第二和第四电阻器元件之间以及第二和第四电阻器元件之间形成低电阻触点。 第二和第三电阻器元件比第一电阻器元件宽，并且向第一电阻器元件提供低电阻触点。 这为电阻器提供了低电阻系数和热处理稳定性。

    High density stacked MIM capacitor structure
    9.
    发明授权
    High density stacked MIM capacitor structure 有权
    高密度堆叠MIM电容器结构

    公开(公告)号：US06426250B1

    公开(公告)日：2002-07-30

    申请号：US09863225

    申请日：2001-05-24

    申请人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

    发明人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

    IPC分类号： H01L218242

    CPC分类号： H01L28/90 ,  Y10S438/957

    摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

    摘要翻译： 在第一电介质层中形成第一金属插头。 产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。 第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。 电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。 在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。