公开(公告)号：US20050095727A1

公开(公告)日：2005-05-05

申请号：US10701824

申请日：2003-11-05

申请人： Weng Chang ,  Chih-Cheng Lu ,  Chu-Yun Fu ,  Syun-Ming Jang

发明人： Weng Chang ,  Chih-Cheng Lu ,  Chu-Yun Fu ,  Syun-Ming Jang

IPC分类号： H01L21/762 ,  H01L23/544 ,  H01L21/66 ,  G01R31/26 ,  H01L21/76

CPC分类号： H01L22/34 ,  H01L21/76229

摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。 每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。 在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US07118987B2

公开(公告)日：2006-10-10

申请号：US10767657

申请日：2004-01-29

申请人： Chu-Yun Fu ,  Chih-Cheng Lu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Chih-Cheng Lu ,  Syun-Ming Jang

IPC分类号： H01L21/76

CPC分类号： H01L21/76235 ,  A61F2/958 ,  A61F2002/9583 ,  A61F2250/0098 ,  A61M25/001 ,  A61M25/005 ,  A61M25/0054 ,  A61M25/0068 ,  A61M25/0069 ,  A61M25/008 ,  A61M25/0108 ,  A61M25/0127 ,  A61M25/1027 ,  A61M2025/1079 ,  A61M2025/1093 ,  A61M2205/32

摘要： A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.

摘要翻译： 一种浅沟槽隔离（STI）结构及其形成方法，其具有减小的应力以改善电荷迁移率，该方法包括提供包括覆盖在半导体衬底上的至少一个图案化硬掩模层的半导体衬底; 根据所述至少一个图案化硬掩模层干蚀刻所述半导体衬底中的沟槽; 形成一个或多个衬垫层以使选自二氧化硅，氮化硅和氮氧化硅的沟槽的沟槽; 形成包含二氧化硅的一层或多层沟槽填充材料以回填沟槽; 进行至少一个热退火步骤以缓和沟槽填充材料中的累积应力; 执行CMP和干蚀刻工艺中的至少一个以去除沟槽高度上的多余沟槽填充材料; 以及去除所述至少一个图案化的硬掩模层。

公开(公告)号：US07002177B2

公开(公告)日：2006-02-21

申请号：US10701824

申请日：2003-11-05

申请人： Weng Chang ,  Chih-Cheng Lu ,  Stacey Fu ,  Syun-Ming Jang

发明人： Weng Chang ,  Chih-Cheng Lu ,  Stacey Fu ,  Syun-Ming Jang

IPC分类号： H01L23/58 ,  H01L27/14 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L21/76229

摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。 每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。 在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US07098116B2

公开(公告)日：2006-08-29

申请号：US10753816

申请日：2004-01-08

申请人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Syun Ming

发明人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Syun Ming

IPC分类号： H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76229

摘要： A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

摘要翻译： 描述了一种降低包括密集沟槽阵列和宽沟槽的STI图案中的氧化物厚度变化的方法。 使用沉积/溅射（D / S）比为9.5的第一HDP CVD步骤沉积厚度为浅沟槽深度的120至130％的电介质层。 在具有NF 3，SiF 4或NF 3 Si和SiF 4的相同CVD室中进行回蚀刻， 以去除初始介电层的约40至50％。 D / S比为16的第二HDP CVD步骤将附加的电介质层的厚度沉积到稍高于第一次沉积后的水平。 回蚀刻和第二沉积形成较平滑的介电层表面，其使得随后的平坦化步骤能够在宽的沟槽中提供最少量的凹陷的填充的STI特征。

公开(公告)号：US20050153519A1

公开(公告)日：2005-07-14

申请号：US10753816

申请日：2004-01-08

申请人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Ming

发明人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Ming

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76229

摘要： A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

摘要翻译： 描述了一种降低包括密集沟槽阵列和宽沟槽的STI图案中的氧化物厚度变化的方法。 使用沉积/溅射（D / S）比为9.5的第一HDP CVD步骤沉积厚度为浅沟槽深度的120至130％的电介质层。 在具有NF 3，SiF 4或NF 3 Si和SiF 4的相同CVD室中进行回蚀刻， 以去除初始介电层的约40至50％。 D / S比为16的第二HDP CVD步骤将附加的电介质层的厚度沉积到稍高于第一次沉积后的水平。 回蚀刻和第二沉积形成较平滑的介电层表面，其使得随后的平坦化步骤能够在宽的沟槽中提供最少量的凹陷的填充的STI特征。

公开(公告)号：US07872913B2

公开(公告)日：2011-01-18

申请号：US12758760

申请日：2010-04-12

申请人： Cheng-Da Huang ,  Chih-Cheng Lu ,  Hsin Chen

发明人： Cheng-Da Huang ,  Chih-Cheng Lu ,  Hsin Chen

IPC分类号： G11C16/04

CPC分类号： G11C27/005 ,  G11C16/0441

摘要： A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor, a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage.

摘要翻译： 非易失性模拟存储器具有浮动栅极点。 非易失性模拟存储器包括电容器，第一电流源，第二电流源和电流调节器。 第一电流源由浮动栅极点处的电压值控制并产生第一电流。 第二电流源由浮动栅极点处的电压值控制并产生第二电流。 电流调节器接收输出电压和参考电压，并根据输出电压和参考电压调整第一电流和第二电流。 电流调节器对电容器充电或放电，以使输出电压与参考电压相等。

公开(公告)号：US20050238073A1

公开(公告)日：2005-10-27

申请号：US10824838

申请日：2004-04-15

申请人： Peidong Wang ,  Chih-Cheng Lu ,  Daryoosh Vakhshoori

发明人： Peidong Wang ,  Chih-Cheng Lu ,  Daryoosh Vakhshoori

IPC分类号： H01S5/00 ,  H01S5/028 ,  H01S5/0625 ,  H01S5/10 ,  H01S5/34

CPC分类号： B82Y20/00 ,  H01S5/028 ,  H01S5/06255 ,  H01S5/101 ,  H01S5/1057 ,  H01S5/34 ,  H01S5/3413 ,  H01S2301/04

摘要： Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap. Method for forming semiconductor substrate is disclosed, comprising providing wafer having quantum wells having given bandgap, depositing cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap.

摘要翻译： 公开了具有量子阱具有第一带隙的半导体衬底，以及具有小于第二带隙的第二带隙的量子阱。 公开了半导体结构，其包括具有给定带隙的量子阱的衬底，其他量子阱被修改为具有大于给定带隙的带隙。 公开了半导体衬底，其包括具有量子阱的晶片，第一带隙的截面以及大于第一带隙的第二带隙的截面。 提供了形成半导体衬底的方法，其包括提供具有给定带隙的晶片，在部分上沉积介电帽和快速热退火至大于给定带隙的调谐带隙。 公开了半导体结构，其包括具有通过沉积帽和快速热退火而修改的量子阱的衬底，所述量子阱具有大于给定带隙的调谐带隙。 公开了一种用于形成半导体衬底的方法，其包括提供具有给定带隙的量子阱的晶片，将部分上的沉积帽和快速热退火至大于给定带隙的调谐带隙。

公开(公告)号：US20090257276A1

公开(公告)日：2009-10-15

申请号：US12192137

申请日：2008-08-15

申请人： Cheng-Da Huang ,  Chih-Cheng Lu ,  Hsin Chen

发明人： Cheng-Da Huang ,  Chih-Cheng Lu ,  Hsin Chen

IPC分类号： G11C27/00 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C27/005 ,  G11C16/0441

摘要： A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current.

摘要翻译： 非易失性模拟存储器具有浮动栅极点。 非易失性模拟存储器包括第一电流源，第二电流源和电流调节器。 第一电流源产生第一电流，第二电流源产生第二电流。 电流调节器根据参考电流和第一电流打开或关闭第二电流的电流路径。 此外，当第二电流的电流路径导通时，根据第二电流来调节第一电流，使得第一电流等于参考电流。

公开(公告)号：US06693047B1

公开(公告)日：2004-02-17

申请号：US10324532

申请日：2002-12-19

申请人： Chih-Cheng Lu ,  Wen Chang ,  Syun-Ming Jeng

发明人： Chih-Cheng Lu ,  Wen Chang ,  Syun-Ming Jeng

IPC分类号： H01L2131

CPC分类号： H01L21/02079 ,  H01L21/02032 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633

摘要： A method for removing at least one carbon doped oxide layer over a surface to recycle the semiconductor process wafer including providing a semiconductor wafer including a process surface including at least one carbon doped silicon oxide layer; oxidizing the carbon doped oxide layer according to an oxidizing treatment to convert at oxidize at least a portion of the carbon doped oxide layer to produce silicon oxide; and, wet etching the silicon oxide to substantially remove the silicon oxide.

摘要翻译： 一种用于在表面上去除至少一个碳掺杂氧化物层以再循环半导体工艺晶片的方法，包括提供包括至少一个碳掺杂氧化硅层的工艺表面的半导体晶片; 根据氧化处理氧化碳掺杂的氧化物层以在氧化至少一部分碳掺杂的氧化物层以转化以产生氧化硅; 并湿法蚀刻氧化硅以基本上去除氧化硅。

公开(公告)号：US08692571B2

公开(公告)日：2014-04-08

申请号：US13183521

申请日：2011-07-15

申请人： Fang-Shi Jordan Lai ,  Chih-Cheng Lu ,  Yung-Fu Lin ,  Hsu-Feng Hsueh ,  Chin-Hao Chang ,  Cheng Yen Weng ,  Manoj M. Mhala

发明人： Fang-Shi Jordan Lai ,  Chih-Cheng Lu ,  Yung-Fu Lin ,  Hsu-Feng Hsueh ,  Chin-Hao Chang ,  Cheng Yen Weng ,  Manoj M. Mhala

IPC分类号： G01R31/00 ,  G01R31/319

CPC分类号： G01R31/31924 ,  G01R31/2642

摘要： The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

摘要翻译： 集成电路的可靠性是根据样品金属氧化物半导体（MOS）器件的可操作特性推断的，该器件可以切换地耦合到漏极/源极偏置和栅极输入电压，这些标称电压和电流条件会提高应力并引起临时或永久性降解 ，例如热载流子注入（HCI），偏置温度不稳定性（BTI，NBTI，PBTI），时间依赖介电击穿（TDDB）。 所测试的MOS器件（优选同时或同时测试的PMOS和NMOS器件）被配置为向具有级联的反相器级的环形振荡器供电的电流源，从而改变振荡器频率作为应力的影响的量度 在被测设备上，但不会升高施加到逆变器级的应力。